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Measurements >> RF Measurements >> Phase margin estimation for switched capacitor circuits
https://designers-guide.org/forum/YaBB.pl?num=1264078269

Message started by shaikh_sarfraz on Jan 21^st, 2010, 4:51am

Title: Phase margin estimation for switched capacitor circuits
Post by shaikh_sarfraz on Jan 21^st, 2010, 4:51am

Hi,
I want to find the phase margin of a switched capacitor based voltage regulator(buck type). Switching frequency of 1MHz.

I found that we can use PSS+PAC analysis for this.
However once I do PSS+PAC analysis, I can get the phase plot of the carrier and other harmonics.

If this is the correct approach then how can we extract the phase margin from the PAC analysis?

Best Regards
Sarfraz

Title: Re: Phase margin estimation for switched capacitor circuits
Post by pancho_hideboo on Jan 21^st, 2010, 5:44am

Your questions are no more than usage of very specific vendor's simulator.
There is no issue related to "RF Measurement".
Please post to "Simulator's Board" not "Measurement's Board".

Your following post is also not related to "Measurement".
http://www.designers-guide.org/Forum/YaBB.pl?num=1262097621

What vendor's simulator do you use ?
There are many simulators which have analyses called as PSS, PAC and Pnoise.

If you use Cadence Spectre, use PSS/PSTB.

Title: Re: Phase margin estimation for switched capacitor circuits
Post by shaikh_sarfraz on Jan 21^st, 2010, 8:51am

thanks for the help.........pss/pstb works
I am indeed using cadence spectre rf.

And sorry for posting it in the wrong section.

Best Regards
Sarfraz