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Simulators >> AMS Simulators >> speed up the NCsim elaboration process?
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Message started by ln3 on Mar 19^th, 2010, 3:59am

Title: speed up the NCsim elaboration process?
Post by ln3 on Mar 19^th, 2010, 3:59am

Hi there

I am currently simulating the Top level of a mixed signal chip. The digital parts are synthesized verilog netlist and the analog part has been completly modeled using Verilog-AMS. Currently, we are using IUS/Incisive 92.
Since the digital part in the testbench wont change, is there anyway to speed up the elaboration process? can't find any ncelab command for that.
Thanks in advance for your help!

Title: Re: speed up the NCsim elaboration process?
Post by Andrew Beckett on Mar 19^th, 2010, 10:58am

Which flow are you using (OSS/irun or CellBased/three-step (ADE or HED))?

The elaboration is much quicker using the irun flow.

You don't give much info - how long is it spending in elaboration?

More of a tool issue - this probably would have been better in the AMS Simulators board (I suspect Ken will move it there).

Regards,

Andrew.

Title: Re: speed up the NCsim elaboration process?
Post by ln3 on Mar 19^th, 2010, 11:28am

Andrew Beckett wrote on Mar 19^th, 2010, 10:58am:

Thank you for the answer Andrew.
Currently I am using HED Cell based three step flow, elaboration took almost 15 min to finish and is not really multi core capable. I have changed OSS/irun in the ADE one time, but it throws me a netlist error event the netlist log shows no errors....

Title: Re: speed up the NCsim elaboration process?
Post by Andrew Beckett on Mar 21^st, 2010, 3:43am

One way to make the conventional three-step elaboration quicker is to limit the number of libraries in your cds.lib (not always possible).

Anyway, I'd suggest you contact Cadence Customer Support - that way we can work through this carefully and with the full information of what you're trying to do (and file a CCR if there's a bug or enhancement needed).

Regards,

Andrew.

Title: Re: speed up the NCsim elaboration process?
Post by ln3 on Apr 9^th, 2010, 8:05am

Hello Andrew,
THank you very much for the replies. Using the OSS based netlist do give me some speed ups, but the oss netlist and ncvlog has problem with modules using 2-D arrays like
----
module test(\out1[5])
output [3:0] \out1[5]
....
endmodule
----
is ther any work around for this?

Title: Re: speed up the NCsim elaboration process?
Post by Andrew Beckett on Apr 11^th, 2010, 8:05am

That looks very odd - I'm not sure why such a net name would be escaped. Without knowing what the design looks like and which version you're using, hard to know the root cause and if there's a fix or workaround.

I would suggest you contact Cadence Customer Support.

Regards,

Andrew.