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https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> StrongArm Comparator Gain https://designers-guide.org/forum/YaBB.pl?num=1272909056 Message started by Ruritania on May 3rd, 2010, 10:50am |
Title: StrongArm Comparator Gain Post by Ruritania on May 3rd, 2010, 10:50am Hi, For the conventional StrongArm comparator (see figure attached below), we know that shortly after the rising edge of ph1, there's an amplification stage between the input (Vin+, Vin-) and output (vo+, vo-), before the regeneration takes over the operation. My question is how to simulate or predict this gain in the simulator, for example, spectre or spectreRF? Thanks. |
Title: Re: StrongArm Comparator Gain Post by pancho_hideboo on May 3rd, 2010, 11:19am I can't find out any design issue in your post. Your question is no more than usage of specific vendor's simulator. http://www.designers-guide.org/Forum/YaBB.pl?num=1245967593/2#2 analyses -> tran -> option -> actimes = 100n acname = ac |
Title: Re: StrongArm Comparator Gain Post by Ruritania on May 3rd, 2010, 3:25pm pancho_hideboo wrote on May 3rd, 2010, 11:19am:
Sorry that I might have posted this at the wrong place. I supposed that people working on High speed I/O design may come across with the same issues. pancho_hideboo wrote on May 3rd, 2010, 11:19am:
I tried, but didn't work (the output gain is like -100dB, obviously not right). Is it because of the dynamic characteristic of this circuit? Thanks. |
Title: Re: StrongArm Comparator Gain Post by pancho_hideboo on May 4th, 2010, 12:34am Ruritania wrote on May 3rd, 2010, 3:25pm:
Try to vary "actimes". You can set time array for "actimes". actimes=[...] ; Times when analyses specified in acname array are performed. Show me your netlist regarding signal sources and tran statement. You must not set large signal sinusoidal for Vin+ and Vin-. |
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