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Design >> High-Speed I/O Design >> PLL-based CDR and PI-based CDR
https://designers-guide.org/forum/YaBB.pl?num=1280203578

Message started by neoflash on Jul 26^th, 2010, 9:06pm

Title: PLL-based CDR and PI-based CDR
Post by neoflash on Jul 26^th, 2010, 9:06pm

Hi,

PLL-based CDR seems to be the main stream in the early days of data com. Recent ten years the PI-based design has appeared to dominate over.

What's the cons and pros of the two different architectures?

Thanks,
Neo

Title: Re: PLL-based CDR and PI-based CDR
Post by casual on Jul 27^th, 2010, 12:23am

PI based designs have two types. One is analog PI and the other one is digital PI. digital PI is favorable and popular since it is robust and no analog filter!! the drawback is the finite resolution.

Title: Re: PLL-based CDR and PI-based CDR
Post by love_analog on Jul 29^th, 2010, 7:08am

Good question..

With PLL based ones, you need to have a PLL for each CDR.

For multi-lane I/O applications and scalability, this is expensive.

people have a central PLL, clock distribution to the I/O lanes and put a PI in each lane to generate the sampling clock.

Title: Re: PLL-based CDR and PI-based CDR
Post by lye on Sep 19^th, 2010, 12:00am

PI-based CDR will generate multi-step phase jumps when input data & local PLL have frequency offset, and will degrade jitter torlerance. If there is different SSC@input data & local PLL, this could be worse. Maybe this is the main weakpoint of PI-baseed CDR. Or there are already some cure for this problem, plz let me know, thanks very much :)

Title: Re: PLL-based CDR and PI-based CDR
Post by love_analog on Oct 11^th, 2010, 6:33am

Typical PI based CDR have a 2nd order loop. The integrating loop will handle the frequency difference.
So Jitter tolerance is not degraded

Title: Re: PLL-based CDR and PI-based CDR
Post by SATurn on May 18^th, 2011, 2:33pm

Hi,

Just a short addition: PLL-based CDR provides the possibility of recovering the frequency while it is limited in the PI-based CDRs.

SATurn

Title: Re: PLL-based CDR and PI-based CDR
Post by BackerShu on Oct 15^th, 2011, 12:29pm

To my certain knowledge,

PLL-based CDR usually encounters a tradeoff between the Jitter Transfer and Jitter Tolerance since their cut frequencies are dependent to each other.
Multichannel Crosstalking, as mentioned above, is also a annoying problem in PLL-based CDR.

PI-based CDR usually is limited by its phase jump, or quantization noise, and multiphase clock routing could also be a problem.

I think both of them could provide clock and data recovery.

Title: Re: PLL-based CDR and PI-based CDR
Post by loose-electron on Oct 23^rd, 2011, 7:47pm

If you already have a common clock using PI is smaller and generally consumes less power.

if you don;t have frequency locked signal avaialble then you need the PLL.