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Simulators >> Timing Simulators >> nanosim memory design
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Message started by seahs on Nov 15^th, 2010, 7:47pm

Title: nanosim memory design
Post by seahs on Nov 15^th, 2010, 7:47pm

how to calculate the sram bitline wiring capacitance ?

It seems the total bitline cap is very small in my design, about 100fF for a bitline with 1024 memory cells connected in 130nm. I am wondering if the metal layer cap is included.

Thanks for any suggestion.