The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> High-Speed I/O Design >> multiple LVDS clock receiver termination
https://designers-guide.org/forum/YaBB.pl?num=1305635045

Message started by XY-oriented on May 17^th, 2011, 5:24am

Title: multiple LVDS clock receiver termination
Post by XY-oriented on May 17^th, 2011, 5:24am

maybe a dumb question but signal integrity and impedance matching are not my strongest :-[ ...
let say I have a differential clock distributed to 4 LVDS receivers (4 ASICs) how should the termination resistor be? I see 2 possibilities:

1- 1 external 100 Ohm at the end of the PCB bus.
2- or each ASIC have a 400Ohm on-chip termination.

is option 2 a good solution ? and should the impedance of each PCB section between 2 ASICs equal 50 Ohm ?

anything to conciser or better solutions?

-thanks

Title: Re: multiple LVDS clock receiver termination
Post by loose-electron on Aug 4^th, 2011, 8:01am

please read up on the topics of transmission lines and termination of transition lines, and characteristic impedance.

Title: Re: multiple LVDS clock receiver termination
Post by harpoon on Aug 19^th, 2011, 7:23am

loose-electron wrote on Aug 4^th, 2011, 8:01am:

please read up on the topics of transmission lines and termination of transition lines, and characteristic impedance.

... and basic LVDS signalling !

Title: Re: multiple LVDS clock receiver termination
Post by rfcooltools.com on Sep 7^th, 2011, 6:13pm

XY-oriented,
out of the two options you propose 2 is the one closer to what you want, but you will still have other issues to resolve.
The transmitter having an output impedance of 100 ohms . The pcb that connects to this will have a characteristic impedance of 100 Ohms. This is not a series impedance but rather a physical characteristic of the type of transmission line. Basically if both sides of this line are 100 ohms then there will be no power lost (at least ideally) and the current and voltage phase relationship will be such that all that occurs is what appears to be a delay. If both sides are not the same then the power is not absorbed by the load, but reflected. The magnitude of the reflection is related to amount of difference from the characteristic impedance of each termination and the length of the line as well as the frequency of the signal. For a digital signal example of a LVDS clock running at 200MHz you will want to preserve several of the odd harmonics in order for it to look like a 200MHz clock on both ends of the transmission line. What will likely happen if the transmission line is not properly terminated is that harmonics will arrive out of phase and out of proportion to the original intended signal.

Where your problem lies is not just at the receiving IC but rather where the transmission needs to split into four 400 Ohm transmission lines. First it will be difficult to make reliable 400 Ohm transmission lines in most pcb substrates (because the dimensions will be approaching the minimum line dimensions and spacing). second you need to handle the transition from 100 to four 400 Ohm lines.
Here are some options:
One way to do this is to incur a loss and use a passive resistor splitter which would give you about 12dB of signal loss. Another would be to use a transformer designed to your specifications and this would be the most ideal way to do it. Another way would be to design an stripline impedance transformer, this would require electromagnetic design expertise and a tool such as Sonnet or HFSS to pull it off.

If you are designing this IC you may want to consider having a repeater on each IC and daisy chaining them together.

Or finally, if your transmitter and recievers are close enough together and your LVDS signal is low enough in frequency you could just try an experiment to see if it works brute force as your suggestion number 2 would.

http://rfcooltools.com