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Other CAD Tools >> Entry Tools >> What is the status of analog automated IC layout?
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Message started by weber8722 on Jul 8^th, 2011, 4:05am

Title: What is the status of analog automated IC layout?
Post by weber8722 on Jul 8^th, 2011, 4:05am

In a recent mixed-signal IC design project (mid-size, no deep-sub-um technology) I used circuit optimization techniques with some success, but the whole analog layout was still done fully manually (just schematic-driven, not more), only routing to the control-unit was done with a routing tool.
As usual I observed that analog layout takes more than expect, but my trials with constraints, analog placers, etc. where not so positive. With no constraints the placements where poor, with many constraints, just many of them are not kept. Or partly the placement was good, but it was extremely difficult to repair the non-optimum parts.
What are your experiences?
Which tools?
PDK support?
Who should use them, the front-end designer or a layout expert? Learning curve?
For what blocks (complexity, ADC, RF,...)?

Bye Stephan

Title: Re: What is the status of analog automated IC layout?
Post by loose-electron on Sep 18^th, 2011, 1:49pm

still largely manual, schematic driven layout, with auto generation of elements using PCell.

Some people try to manually place and then auto-route from there but the autorouter often messes it up even after component placement.

Title: Re: What is the status of analog automated IC layout?
Post by EricF on Sep 21^st, 2011, 2:20pm

We (Ciranova) develop these tools and have a number of tapeouts at advanced geometries. Our experiences:

- Placement is harder to automate but we believe more important
- iPDK or Skill PDK
- Either circuit designer or high-end layout designer
- Most value on big designs (whole ADC ...) and advanced geometries
- Small designs + simple design rules --> manual is very efficient
- 28nm rules --> very complicated for manual layout
- Proper constraint architecture is crucial or people won't use tool
- Doesn't replace knowledgeable designer, but enables designer to
do much more DRC-clean layout and exploration quickly, esp at
40nm and below