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Design >> High-Speed I/O Design >> Change in frequency and current transients
https://designers-guide.org/forum/YaBB.pl?num=1319609150

Message started by bharat on Oct 25^th, 2011, 11:05pm

Title: Change in frequency and current transients
Post by bharat on Oct 25^th, 2011, 11:05pm

I am trying to understand the power supply ripple when the link data rate goes half of its maximum data rate. (data freq=F=data rate/2)
To emulate this real scenario, I am changing the data frequency from 'F' to 'F/2' and then again bringing it back to 'F'.
While capturing the current profile, I am observing that DC current when the data frequency is F < DC current when the data freq is F/2.
To explain the behavior of currents, from F to F/2;
By adding the bypass capacitor, it lowers the on die resonance frequency along with package loop inductance. If the data frequency is F, one would like to push the on die resonant freq much lower and far from the frequency of interest 'F' (may be in the vicinity of F/2).
But, when the data frequency is reduced to F/2, the on-die resonant freq is still F/2. This may lead to supply ripple, followed by erratic current transients.
Is this correct explanation of higher DC current at low frequency as compared to Higher freq?

Regards,
-Bharat

Title: Re: Change in frequency and current transients
Post by raja.cedt on Oct 26^th, 2011, 12:57am

hello Bharat,
Are you talking about serial IO? and are you testing complte TX,RX,PLL?

because it's difficult to say about DC current at data rates, for example to run at lower data rate, you need to reduce the PLL frequency and unfortunatly if it LC vco i am sure you have to burn more bias current at lower frequency, and hope all other digital guys takes less power and i didn't understand how you are sweeping your data rate man..like sweeping from f/2 to f and again back f..

Thanks,
raj.

Title: Re: Change in frequency and current transients
Post by bharat on Oct 26^th, 2011, 3:09am

Raj,
Yes I am talking about serial IO and simulating ONLY RX.
Assuming the PRBS data coming from TX with the data freq F and F/2.

I am changing the PLL settings to have throughput clock to sample the data at frequency F and F/2. Since the CDR is shut down, I am changing the clk frequency on-the-fly as a stimulus.

I am changing the data freq from F to F/2 because the serial IO has to support the legacy and some customers may want to use at different data rate i.e. half rate/quarter rate etc. Not only this, one may need to vary the data rate as the part of testing mode. I want to study the supply noise and jitter specs because of change in frequency rate.

The VCO is LC based but we are not concerned of power consumption.

Please let me know, if you have further questions to answer my question :)

Thanks

Title: Re: Change in frequency and current transients
Post by loose-electron on Oct 26^th, 2011, 12:49pm

since this is a simulation, why can't you just find where the currents are going in the simulation using the tools available?