The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> High-Speed I/O Design >> Static frequency divider in SiGe tech https://designers-guide.org/forum/YaBB.pl?num=1321474377 Message started by raja.cedt on Nov 16th, 2011, 12:12pm

 Title: Static frequency divider in SiGe tech Post by raja.cedt on Nov 16th, 2011, 12:12pm hello all,i am new to BiCmos technology, is any one know the purpose of the splitt resisters in latch? Please find the attched fig for ref.Thanks,raj.

 Title: Re: Static frequency divider in SiGe tech Post by loose-electron on Nov 18th, 2011, 9:49am Old method of ECL latch.Your latching mechanism feeds back a bias to shift the collectors of the input device.Go digging in literature for ECL latch structures, probably in IEEE journals from 1970 era, or look into the Motorola 10,000 series ECL documents, from the same time period.The circuit is part analog and part digital, so to speak.

 Title: Re: Static frequency divider in SiGe tech Post by raja.cedt on Nov 19th, 2011, 3:08am Thanks loose-electron,I have tried but could n't get any document, so could you please provide any doc or just explain the principle behind this?Thanks,Raj.

 Title: Re: Static frequency divider in SiGe tech Post by loose-electron on Nov 19th, 2011, 6:11pm You get the summation of two currents on the resistors. One current set is due to logic in and clock state, the other one is due to the current state of the data out.When the logic in or clock is released the present state of the voltage is held on the resistors by the state of the data out signals at that point in time.Set up a simple transient simulation and the functionality will be apparent.

 Title: Re: Static frequency divider in SiGe tech Post by loose-electron on Nov 19th, 2011, 6:43pm one additional item - the split resistors are largely a level shifting and gain type of tool. If you are familiar with these devices where they don't use 4 resistors and just use 2, the functionality is essentially the same.