The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Simulators >> Timing Simulators >> UltrasimVerilog error: failed to parse the netlist
https://designers-guide.org/forum/YaBB.pl?num=1326438060

Message started by ahhfyz on Jan 12^th, 2012, 11:00pm

Title: UltrasimVerilog error: failed to parse the netlist
Post by ahhfyz on Jan 12^th, 2012, 11:00pm

Hi, everyone!
I have a system including verilog (modules and sub-modules) and schematic. It can be simulated in SpectreVerilog, but failed in UltrasimVerilog:
"Error found by UltraSim.
ERROR (USIM-18610): The UltraSim simulator failed to parse the netlist.
Correct the above errors and run the simulation again."

What should I do next? Thank you!

Title: Re: UltrasimVerilog error: failed to parse the netlist
Post by AMS_ei on Aug 2^nd, 2016, 4:49am

Hi,

Please use the following two lines and check if it works.

-sysv_ext +.v
-simcompatible_ams spectre

Thank you.