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Modeling >> Passive Devices >> Resistor Modeling with look up table approach
https://designers-guide.org/forum/YaBB.pl?num=1344693688

Message started by Ganesh70508 on Aug 11^th, 2012, 7:01am

Title: Resistor Modeling with look up table approach
Post by Ganesh70508 on Aug 11^th, 2012, 7:01am

I want to design a simple resistor in verilog-A i used following verilog code
//------------------------------------------------------------------------------------------------
`include "constants.vams"
`include "disciplines.vams"
module Table_NL_Resistor(a,b);
inout a;
inout b;
electrical a,b;
parameter real k = 0 from [0:inf);
analog begin
V(a,b) <+ k*$table_model(I(a,b),"sample.dat");
end
endmodule
//------------------------------------------------------------------------------------------------

i tried to simulate above model in cadence spectre it works fine when i connect current source in series with above resistor. Voltage and current Waveform appear properly after simulation

but while simulating using Voltage source in series with above element no Waveform shows up at the output.

how do i overcome above limitation ...?

how can i model such elements in verilogA using look up table based approach ..?

plz Suggest

Thank You,
Ganesh

:)

Title: Re: Resistor Modeling with look up table approach
Post by boe on Aug 13^th, 2012, 10:15am

Ganesh70508 wrote on Aug 11^th, 2012, 7:01am:

... but while simulating using Voltage source in series with above element no Waveform shows up at the output.
...

plz Suggest

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