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Design >> High-Speed I/O Design >> Delay Locked Loop Design
https://designers-guide.org/forum/YaBB.pl?num=1366803388

Message started by saurabh3488 on Apr 24^th, 2013, 4:36am

Title: Delay Locked Loop Design
Post by saurabh3488 on Apr 24^th, 2013, 4:36am

Hi All,

I am working on Delay locked loop design for 200MHz clock.
Using Maneatis architecture. I have some doubt related to design,
please help me regarding this :
1. What does it mean by symmetric load.
2. How to size (W/L) of the symmetric load.
3. It's is said that swing will be symmetric at VControl/2 . but in my design i am not getting this.

please help....

Title: Re: Delay Locked Loop Design
Post by saurabh3488 on Apr 24^th, 2013, 4:37am

V-I curve of symmetric load.

Title: Re: Delay Locked Loop Design
Post by tm123 on Jul 22^nd, 2013, 9:24am

saurabh3488,

Without analyzing it, the circuit you have shown appears to be a way of implementing a PMOS active load. I think the traditional implementation would require a separate bias branch and common mode feedback, but in this case neither seems to be required.

Hope this helps.

Tim