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Design Languages >> VHDL-AMS >> VHDL-AMS file read_write error
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Message started by Milind Shende on Oct 7th, 2013, 6:26am

Title: VHDL-AMS file read_write error
Post by Milind Shende on Oct 7th, 2013, 6:26am

Hello Experts,

I have formed a very simple code. The code reads the file, if it reads 1 then it writes 3 in another file and if 0 then it writes 7 in another file. Code is as follows:


entity node2 is
 
end node2;

architecture behv of node2 is

 signal clk : std_logic := '0';
 
begin  -- behv

 clock_gen: process(clk) is --ref: page 143 system designer's guide to VHDL-AMS
 begin
   if clk = '0' then
     clk <= '1', '0' after 50 us;
   end if;
 end process clock_gen;

 data_log: process is

   file input_file : text open read_mode is "node1_out.txt";
   variable read_line : line;          -- read line string
   variable input_param : bit;   -- read input parameter

   file output_file : text open write_mode is "node2_out.txt";
   variable write_line : line;         -- write output line
   variable output_vtg : integer;      -- write output voltage

 begin

   if clk'event and clk = '1' then
     readline(input_file,read_line);
     read(read_line, input_param);

     if input_param = '1' then
       output_vtg := 3 ;
       write(write_line,output_vtg);
       writeline(output_file,write_line);
     end if;

     if input_param = '0' then
       output_vtg := 7;
       write(write_line, output_vtg);
       writeline(output_file, write_line);
     end if;
     
   end if;

   wait on clk;
 end process;
 
end behv;


In the same folder I have a file named node1_out.txt, which has only one element in the top left corner of the file as 1 without single quotation mark.


The Mentors Advance MS simulator gives me following error:

# ** Error: in Top Vhdl-Ams (behv/node2), process data_log at line 24, in the file /mntsse/escience/shende/.SLinux5/Desktop/CNT_Forschung/TP2/co-sim/scams_model/node2.vhd
# ** Error: Textio error : read bit : the line "read_line" is empty
# Occurred at time 50 us
# ** Error: Simulation failed

Any guesses ???

thanks in Advance,
regards,
Milind.

Title: Re: VHDL-AMS file read_write error
Post by Milind Shende on Oct 10th, 2013, 2:39am

the problem is solved

I replaced the part of code with following lines:

 if clk'event and clk = '1' then
     readline(input_file,read_line);
     read(read_line, input_param, read_ok);

     if not read_ok then
       report "Error reading a bit value from file" severity warning;
     end if;

all the other code remains same.
and the problem is solved ..... :)

thanks for following.
regards,
Milind

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