The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Other CAD Tools >> Entry Tools >> Interaction between blocks and analoglib
https://designers-guide.org/forum/YaBB.pl?num=1393958651

Message started by Davivilla on Mar 4^th, 2014, 10:44am

Title: Interaction between blocks and analoglib
Post by Davivilla on Mar 4^th, 2014, 10:44am

Hi,

I am using cadence IC 5.10 for create verilog-a model.
But when i try to mix verilog-a and elements of analoglib or other lib,
there is no interaction.

i have attached a screen of a simple circuit.
when i simulate to see the potencial or flow. Apparently does not recognize the R0 r:1k from analoglib.

Thank you

Title: Re: Interaction between blocks and analoglib
Post by Andrew Beckett on Mar 5^th, 2014, 1:51am

It's highly likely that there's something wrong with your resistor verilogA model, rather than it being a problem with the analogLib res component (which just netlists to a spectre resistor component). That said, the fact that your VerilogA model is also called resistor might case problems because it clashes.

I just tried this. If I look at my netlist, I get this:

I2 (net4 0) resistor R=20
I1 (pos net4) resistor R=100
R0 (net4 0) resistor r=1K
V0 (pos 0) vsource type=sine ampl=100m freq=100K

If your VerilogA module has a parameter with a capital R, then the r=1k on the primitive resistor will be ignored and the default value will be used.

Note that spectre reports this:

Warning from spectre during circuit read-in.
WARNING (SFE-2654): VerilogA module `resistor' override primitive/(verilogA module) `resistor'.

So that's my guess at what's happening, based on the limited information that you've provided.

Not sure this is really an "Entry Tools" problem, but Ken can move the post if he sees fit.

Regards,

Andrew.

Title: Re: Interaction between blocks and analoglib
Post by Andrew Beckett on Mar 5^th, 2014, 1:53am

Er, whoops - it was Ken who moved it into Entry Tools in the first place. Sorry :'(

Andrew.

Title: Re: Interaction between blocks and analoglib
Post by Davivilla on Mar 6^th, 2014, 1:03pm

Hi Andrew,

You are rigth, i changed the name and parameter of the model resistor it works !!! Thank you.

Now i have another question. i try with a opamp model:

`include "constants.vams"
`include "disciplines.vams"

module CommonSource_VA_simple(IN, OUT);
inout IN, OUT;
electrical IN, OUT;
parameter real ganancia=1.8464;

analog begin
V(OUT) <+ V(IN)*(-ganancia)+3.76;
end

endmodule

At the output of the model i need to see the bandwidth then i put a capacitor of analoglib.
But the same problem appears. The capacitor does not interact with the model of verilog-a.
According to the simulation I have an infinite bandwidth.

what do you think is the problem with this interaction?

Title: Re: Interaction between blocks and analoglib
Post by Davivilla on Mar 6^th, 2014, 1:11pm

This is my simulation.
Both are analyzed in the "out" of the mode.
AC an transiet.

Title: Re: Interaction between blocks and analoglib
Post by boe on Mar 7^th, 2014, 12:28am

Davivilla,
your model describes a voltage-controlled voltage source. So, of course the gain does not depend on frequency or load cap.
- B O E

Title: Re: Interaction between blocks and analoglib
Post by Davivilla on Mar 10^th, 2014, 4:52am

I really appreciate this.
Thank you very much.

Did I want to know if you can help me with a design in this topic?

Best regards

Title: Re: Interaction between blocks and analoglib
Post by Davivilla on Apr 7^th, 2014, 4:25pm

Hi,

how can i do an interaction with other components?
i have tried for a long time and i dont know how to do.
please ! !

Thanks

Title: Re: Interaction between blocks and analoglib
Post by Andrew Beckett on Apr 8^th, 2014, 2:03am

Unless you describe what behaviour you are trying to model when you talk about "interaction with other components", it's rather hard to give some pointers!

Andrew.

Title: Re: Interaction between blocks and analoglib
Post by Davivilla on Apr 9^th, 2014, 3:12pm

Yes sorry,

I'm trying to do a model with multiple assignments to a port out through
V ( out ). that is for example

V(out)<+ 5:
V(out)<+ganancia*laplace_np(V(pos, neg),{1},{-6.28e6, 0, -6.28e9,0});
.
.
.

All the model is behavioral. there is not structural modeling.
For example.
I need the model interacts with an output load and see how it affects the AC response.|

I need a way to read the output load in order to introduce this to the model.

Thank you.

Title: Re: Interaction between blocks and analoglib
Post by Lucho on Apr 9^th, 2014, 8:18pm

So basically what you are trying to say is that you need a way to introduce whatever is at the load of your model within the statement of your laplace filter. In other words , you need to define the frequency of your poles based on the values of capacitance and resistance seen at the output node right ?

If that is the case, as an alternative way I wonder whether the frequency response of such a model would be properly defined if you have two different contribution statements; one using your laplace filter for the "internally" defined frequency response and another one based on the fundamental equations governing R's, C's and L's.

I'll take a look at it and report on findings.

Regards,

Lucho.

Title: Re: Interaction between blocks and analoglib
Post by Andrew Beckett on Apr 9^th, 2014, 11:08pm

The thing is that you are still describing an ideal voltage source - unless your model has some kind of output impedance it won't be affected by the load. If you don't know how your output looks like from an electrical perspective, then I'm not sure how you would expect to see the effect of the load on your system.

Regards,

Andrew.

Title: Re: Interaction between blocks and analoglib
Post by Davivilla on Apr 10^th, 2014, 1:36pm

Hi Andrew,

I totally understand, but could you give me an example?.
What do you recommend for define output impedance to the next model?

Code:

// VerilogA for zamplificador, opamp_designers_guide, veriloga

`include "constants.vams"
`include "disciplines.vams"

module opamp_designers_guide(pos, neg, out);
output out;
input pos,neg;
electrical pos, neg, out;
parameter gain=10;

analog begin
V(out)<+gain*(laplace_np(V(pos,neg),{1},{-6.28e3,0,6.28e12,0}));
end
endmodule

Title: Re: Interaction between blocks and analoglib
Post by Lucho on Apr 10^th, 2014, 1:56pm

Now I am interested in knowing if there is a way in which you could convert

Davivilla wrote on Apr 10^th, 2014, 1:36pm:

V(out)<+gain*(laplace_np(V(pos,neg),{1},{-6.28e3,0,6.28e12,0}));

into

V(out)<+gain*(laplace_np(V(pos,neg),{1},{-6.28e3,0,-1/(2*pi*Rout*Cout),0}));

Where Rout and Cout are external (not in the verilog-a model) components connected to the output node of your amplifier. In this way, your AC response would reflect the impact of the load.