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Modeling >> Semiconductor Devices >> mosfet stress of vbs
https://designers-guide.org/forum/YaBB.pl?num=1394692097

Message started by baohulu on Mar 12^th, 2014, 11:28pm

Title: mosfet stress of vbs
Post by baohulu on Mar 12^th, 2014, 11:28pm

hi, all
in tsmc 40nm pdk model, I find its stress requirement. it is attached below.
my question is why "vbs" is limited to +/- 1.2*Vdd.
vbs is a pn junction , so it can hold high reverse biased voltage, right???

Title: Re: mosfet stress of vbs
Post by Geoffrey_Coram on Mar 24^th, 2014, 12:34pm

You should be careful about posting confidential information on a public forum; it's best not to identify the exact foundry and process node (a pdk for a fine-line cmos process at a large foundry ...).

Title: Re: mosfet stress of vbs
Post by Geoffrey_Coram on Mar 24^th, 2014, 12:36pm

The picture you posted looks to talk about model validity, not stress limits. Generally, foundries don't want to guarantee model accuracy over ranges where they have not measured.