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Modeling >> Semiconductor Devices >> How to calculate the Cp between p substrate and deep Nwell?
https://designers-guide.org/forum/YaBB.pl?num=1397840016

Message started by Jacki on Apr 18^th, 2014, 9:53am

Title: How to calculate the Cp between p substrate and deep Nwell?
Post by Jacki on Apr 18^th, 2014, 9:53am

Hello,

I want to estimate the total parasitic capacitance between the p substrate and deep Nwell. In the layout extraction, the design kits only support the diode extraction, but the parasitic capacitance is not well modeled. So I want to roughly calculate the parasitic capacitance. Can anybody recommend some unit cap value? I am using 0.18um CMOS technology.
Thank you.

Title: Re: How to calculate the Cp between p substrate and deep Nwell?
Post by Jacki on Apr 19^th, 2014, 10:31am

By the way, how is the PN junction capacitance (Cj) changed for different CMOS technologies, like from 0.25um CMOS to 65nm CMOS? Is the unit Cj becoming larger for advanced CMOS technology like 65nm CMOS than the old CMOS technology?

Title: Re: How to calculate the Cp between p substrate and deep Nwell?
Post by Geoffrey_Coram on Apr 22^nd, 2014, 1:12pm

Doesn't the diode extraction include the junction capacitance? I would expect it to be bias-dependent and change with the VDD applied to the nwell.

Title: Re: How to calculate the Cp between p substrate and deep Nwell?
Post by Jacki on Apr 23^rd, 2014, 4:17pm

Geoffrey_Coram wrote on Apr 22^nd, 2014, 1:12pm:

Doesn't the diode extraction include the junction capacitance? I would expect it to be bias-dependent and change with the VDD applied to the nwell.

Hello Geoffrey_Coram,

Only the devices are modeled with this junction diode, but in the region where MIM cap and guarding ring, it is not modeled. So in the parasitic extration, the total parasitic PN junction cap is not acturate.

Title: Re: How to calculate the Cp between p substrate and deep Nwell?
Post by Geoffrey_Coram on Jul 8^th, 2014, 7:34am

Jacki wrote on Apr 23^rd, 2014, 4:17pm:

Only the devices are modeled with this junction diode, but in the region where MIM cap and guarding ring, it is not modeled.

I'm not sure I understand what you're saying. I think you mean, in the extraction, the junction diode is only extracted under MOSFET devices (I guess it's NMOS in deep nwell). And the extraction does not include the diode under MIM caps or guard rings.

Do you know the doping level of the psub or dnw? Can you make some estimates of the capacitance based on the extraction of junction diodes under differently-sized MOS devices?