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https://designers-guide.org/forum/YaBB.pl Other CAD Tools >> Entry Tools >> Virtuoso & Verilog/VHDL https://designers-guide.org/forum/YaBB.pl?num=1406124644 Message started by tdlrali on Jul 23rd, 2014, 7:10am |
Title: Virtuoso & Verilog/VHDL Post by tdlrali on Jul 23rd, 2014, 7:10am Hi all, I'd like to use either Verilog or VHDL to describe testbenches in Virtuoso (IC6.1.5). I've successfully simulated a VerilogA module in spectre, but still I have a few questions. 1) Does Spectre only support VerilogA? Do I have to use the AMS simulator (from IUS) to use VerilogAMS / VHDL-AMS? 2) What's the status/support of the different languages - VerilogA, VerilogAMS, VHDL-AMS? Ideally, I'd like to use VHDL-AMS, because I personally like VHDL better than Verilog. 3) Can I use generic port widths? The Virtuoso Schematic Editor does not seem to support this... Thanks for your help! |
Title: Re: Virtuoso & Verilog/VHDL Post by boe on Jul 24th, 2014, 1:30am tdlrali wrote on Jul 23rd, 2014, 7:10am:
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