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Measurements >> Phase Noise and Jitter Measurements >> Jitter Simulation for DLL based Frequency Multiplier
https://designers-guide.org/forum/YaBB.pl?num=1408521245

Message started by SAAS on Aug 20^th, 2014, 12:54am

Title: Jitter Simulation for DLL based Frequency Multiplier
Post by SAAS on Aug 20^th, 2014, 12:54am

Hi,

I am working on a DLL based frequency multiplier (Cadence 90nm), in which the input frequency is 250MHz and the desired output is 1GHz.
Since I am new to analog designing so I am a little bit confused how to do the jitter simulation. Anybody can please guide.

Thanks in advance

Title: Re: Jitter Simulation for DLL based Frequency Multiplier
Post by MAB on Oct 14^th, 2014, 9:16pm

Can any body update this, how the jitter simulation is done in the PLL/DLL.
We usually say in PLL high frequency jitter component is removed and limited to LPF BW. Can any body update on jitter analysis.

Thanks,

Title: Re: Jitter Simulation for DLL based Frequency Multiplier
Post by Ken Kundert on Oct 15^th, 2014, 11:44pm

See Predicting the phase noise and jitter of PLL-based frequency synthesizers.

-Ken