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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> How to make a 1:4 demux in VAMS https://designers-guide.org/forum/YaBB.pl?num=1411509945 Message started by wag_master on Sep 23rd, 2014, 3:05pm |
Title: How to make a 1:4 demux in VAMS Post by wag_master on Sep 23rd, 2014, 3:05pm I need a 1:4 demux model (data distributor). The following code doesn't work because the transition statements are in a conditional. Does anyone know how this can be done? Thanks. module muxdr_1_4(Dp, Dn, Rp, Rn, CKp, CKn, D0p, D0n, D1p, D1n, D2p, D2n, D3p, D3n, vcc); input Dp, Dn, Rp, Rn, CKp, CKn, vcc; voltage Dp, Dn, Rp, Rn, CKp, CKn, vcc; output D0p, D0n, D1p, D1n, D2p, D2n, D3p, D3n; electrical D0p, D0n, D1p, D1n, D2p, D2n, D3p, D3n; parameter real vswing = 0.24 from (0:inf); parameter real tdel = 5p from [0:inf); parameter real trise = 10p from (0:inf); parameter real tfall = 10p from (0:inf); real out0p, out0n. out1p, out1n, out2p, out2n, out3p, out3n; integer x, cntr; analog begin @(initial_step) begin cntr = 0; end if (V(Rp) > V(Rn)) cntr = 0; @(cross( V(CKp)-V(CKn), 1 ) ) begin cntr = cntr+1; if (cntr > 3) cntr = 0 end x = V(Dp) < V(Dn); outp = V(vcc)*x + (V(vcc)-vswing) * !x; outn = V(vcc)*!x + (V(vcc)-vswing) * x; case (cntr) 0: begin V(D0p) <+ transition( outp, tdel, trise, tfall); V(D0n) <+ transition( outn, tdel, trise, tfall); end 1: begin V(D1p) <+ transition( outp, tdel, trise, tfall); V(D1n) <+ transition( outn, tdel, trise, tfall); end 2: begin V(D2p) <+ transition( outp, tdel, trise, tfall); V(D2n) <+ transition( outn, tdel, trise, tfall); end 3: begin V(D3p) <+ transition( outp, tdel, trise, tfall); V(D3n) <+ transition( outn, tdel, trise, tfall); end default: $strobe("muxdr_1_4: Help! cntr = %d", cntr); endcase end endmodule |
Title: Re: How to make a 1:4 demux in VAMS Post by Ken Kundert on Sep 23rd, 2014, 8:28pm All the signals other than the supplies appear as if they are digital signals. You claim to want a Verilog-AMS model, but you gave a Verilog-A model. If the model is digital, you should be using Verilog. -Ken |
Title: Re: How to make a 1:4 demux in VAMS Post by wag_master on Sep 24th, 2014, 7:43am It needs to be Verilog-A or AMS because the output needs to be Vcc referenced with a 240 mV swing. I thought AMS was a super-set of Verilog-A? |
Title: Re: How to make a 1:4 demux in VAMS Post by Ken Kundert on Sep 24th, 2014, 8:26am Using Verilog-A for digital signals is slow and tedious. You are better served writing a Verilog model, and then if you need an electrical output, just modifying it so that it produces it. However, if you want to continue to use Verilog-A, you can simply assign to variables in the case statement, and drive the outputs using a transition function applied to the variables outside any conditionals. -Ken |
Title: Re: How to make a 1:4 demux in VAMS Post by wag_master on Sep 24th, 2014, 12:03pm Ken: The problem with that is that the output which gets the transition depends on cntr. How is that done? Do you assign a variable for each output like this: out1p = V(D0p) and so on for all 8 outputs, then use a case statement to change the one that is selected. and then have 8 transition statements after the case? Maybe it would be easier to do what you said- Verilog then convert. That would be done external to the Verilog code? |
Title: Re: How to make a 1:4 demux in VAMS Post by wag_master on Sep 25th, 2014, 8:44am Putting it in Verilog sort of makes things more difficult. It'd need to make a Verilog cell for each function I want to model, then put that inside another cell to convert it from logic to analog. And convert analog to logic at the input. I guess I'd really like to stay with Verilog-A/AMS.... |
Title: Re: How to make a 1:4 demux in VAMS Post by Ken Kundert on Sep 25th, 2014, 8:24pm There is only one function you want to model, and that is your dmux, so there is no need for multiple cells. I do not understand your issue with using verilog-code for most of the model. If you want stick with Verilog-A, you can use 4 variables, and convert to differential signals only when driving the outputs. -Ken |
Title: Re: How to make a 1:4 demux in VAMS Post by wag_master on Sep 26th, 2014, 1:39pm Ken: I am developing a behavioral simulation which will eventually be transistor level and use the same cells and symbols. So it would be nice to stay analog and use the same simulator. I have several other functions I need to model, but the Verilog-A is working for those, so you're right, I only have one function left to model. The reason I'd use two cells is I'd put the Verilog cell inside another cell that would also have the circuits (VCVS) that would convert analog to digital and back. Essentially CML to CMOS and vice versa. Tom |
Title: Re: How to make a 1:4 demux in VAMS Post by wag_master on Sep 26th, 2014, 3:30pm I got it working. Here's the code: `include "discipline.h" `include "constants.h" //-------------------- // demuxdr_1_4 // V1. 9/23/2014 TS // Added reset, made all pins differential except vcc. // Logic is vcc referenced with a pp swing of vswing // // - 1 to 4 demux // This models an active demux, not a t-gate type. // It uses an internal counter instead of external inputs // to determine which output is selected. // // Dp, Dn: Signal to be multiplexed (val) // CKp, CKn: Clock input (val) // Rp, Rn, Sp, Sn: Reset and set inputs (val) // Q0,Q1,Q2,Q3: Outputs (val,flow) // vcc: Supply voltage (val) // // INSTANCE parameters // vswing = p-p output voltage swing // tdel, trise, tfall = the usual [s] // module demuxdr_1_4(Dp, Dn, Rp, Rn, CKp, CKn, Q0p, Q0n, Q1p, Q1n, Q2p, Q2n, Q3p, Q3n, vcc); input Dp, Dn, Rp, Rn, CKp, CKn, vcc; voltage Dp, Dn, Rp, Rn, CKp, CKn, vcc; output Q0p, Q0n, Q1p, Q1n, Q2p, Q2n, Q3p, Q3n; electrical Q0p, Q0n, Q1p, Q1n, Q2p, Q2n, Q3p, Q3n; parameter real vswing = 0.24 from (0:inf); parameter real tdel = 5p from [0:inf); parameter real trise = 10p from (0:inf); parameter real tfall = 10p from (0:inf); real out0p, out0n, out1p, out1n, out2p, out2n, out3p, out3n; real vh, vl; integer x, x0, x1, x2, x3, cntr; analog begin @(initial_step) begin // Since cntr=cntr+1 occurs before the case statement, // this makes the first one selected to be out0. cntr = 3; vh = V(vcc); vl = vh-vswing; out0p = vl; out1p = vl; out2p = vl; out3p = vl; out0n = vh; out1n = vh; out2n = vh; out3n = vh; end if (V(Rp) > V(Rn)) cntr = 3; @(cross( V(CKp)-V(CKn), 1 ) ) begin cntr = cntr+1; if (cntr > 3) cntr = 0; x = V(Dp) > V(Dn); vh = V(vcc); vl = vh-vswing; // Do the demux function case (cntr) 0: begin out0p= vh*x + vl*!x; out0n= vh*!x + vl*x; $strobe("%r: Setting out0", $abstime); end 1: begin out1p= vh*x + vl*!x; out1n= vh*!x + vl*x; $strobe("%r: Setting out1", $abstime); end 2: begin out2p= vh*x + vl*!x; out2n= vh*!x + vl*x; $strobe("%r: Setting out2", $abstime); end 3: begin out3p= vh*x + vl*!x; out3n= vh*!x + vl*x; $strobe("%r: Setting out3", $abstime); end default: $strobe("%r: ***** demuxdr_1_4: Help! cntr = %d", $abstime, cntr); endcase end V(Q0p) <+ transition( out0p, tdel, trise, tfall); V(Q0n) <+ transition( out0n, tdel, trise, tfall); V(Q1p) <+ transition( out1p, tdel, trise, tfall); V(Q1n) <+ transition( out1n, tdel, trise, tfall); V(Q2p) <+ transition( out2p, tdel, trise, tfall); V(Q2n) <+ transition( out2n, tdel, trise, tfall); V(Q3p) <+ transition( out3p, tdel, trise, tfall); V(Q3n) <+ transition( out3n, tdel, trise, tfall); end endmodule |
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