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Measurements >> RF Measurements >> Biasing or supply voltage selection
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Message started by farsheed on Dec 14^th, 2014, 1:56am

Title: Biasing or supply voltage selection
Post by farsheed on Dec 14^th, 2014, 1:56am

In CMOS 130nm cmos process what should be the standard biasing voltage? Is it fixed to 1.2 V or it can be varied up to the level to get the desired output voltage?

Title: Re: Biasing or supply voltage selection
Post by Jeffrey987 on Mar 12^th, 2015, 11:13am

Core transistors typically have a maximum voltage rating between any of the 4 nodes (GDSB). If you exceed this voltage you can have reliability issues. Small overdrives can be tolerated with reliability reduction, Higher voltages cause gate oxide breakdown and finish your transistor directly. Normally you do not want to go above the core voltage.

In some analog circuits and if your CMOS process supports it, you can use deep-nwells to stack transistors and get higher volgages like PA's, otherwise you can use IO transistors that typically support higher volgages (2.5,3.3,5V) but can be slower.