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Analog Verification >> Analog Functional Verification >> Verilog AMS co simulation with SV
https://designers-guide.org/forum/YaBB.pl?num=1424781626

Message started by ranjang on Feb 24^th, 2015, 4:40am

Title: Verilog AMS co simulation with SV
Post by ranjang on Feb 24^th, 2015, 4:40am

Hi all,

I wanted to simulate the verilog ams code with testbench as SV/UVM.

I face some problem but when I simulate with spice and SV its working fine.

Do I need to write amsd{
}
block for running verilog -AMS with SV.

I am using cadence simulator and running the simulation from command line.

Thanks

Title: Re: Verilog AMS co simulation with SV
Post by AMS_ei on Jan 18^th, 2017, 8:04am

Hi,

sv and ams cannot co-exist. You have to remove -sv switch from the irun option if you have used it.

Then it should be compiling fine.

Thank you.

Kind regards,

Title: Re: Verilog AMS co simulation with SV
Post by Andrew Beckett on Jan 20^th, 2017, 9:21am

Note that this last reply was a bit misleading. Verilog-AMS and SystemVerilog can coexist. You should however use the file suffix to determine whether it is compiling Verilog-AMS or SystemVerilog rather than forcing it via a command line option (which would indeed cause a problem). It's not clear whether that was the problem the original poster faced - it was an elderly posting...

Regards,

Andrew