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Modeling >> Semiconductor Devices >> width of the PN junction calculation
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Message started by dog1 on Mar 1st, 2015, 9:57am

Title: width of the PN junction calculation
Post by dog1 on Mar 1st, 2015, 9:57am

I am reading the 4th edition of Analysis and design of analog integrated circuits by Paul Gray. In chapter 1.2, there is a description of the calculation of the width of the depletion region when a reverse bias voltage is added (see attachment). However, I find it confusing. In the calculation, the assumption is that when the reverse voltage VR is added, the total potential difference at the PN junction is Vtot=VR+ψo, where ψo is the built-in potential. Thus the addition of the VR increases Vtot from ψo to VR+ψo. This potential difference is built by the dipoles of charge existing at the junction. Thus the higher the VR, the more dipoles that are needed to build up VR+ψo, which in turn lead to wider depletion region. However, I have a different ideal. I think that
1.      Vtot should not be VR+ψo. I am thinking that this potential should stay at ψo when VR is added. This is because it should counteract the effect of the diffusion of mobile holes and electrons, and the force of diffusion is independent of the VR.
2.      Vtot should not be built by the purely by the dipoles of charge existing at the junction. In fact, I am expecting two parts of Vtot, one from the dipoles of charge existing at the junction, let’s call it ψ, and the other from VR. When VR is larger, to keep Vtot constant, ψ should be smaller, and thus less dipoles of charge is needed in the depletion region, and the width of the region gets smaller.
I don’t know what is wrong with my thinking and why the assumption used in the book is right. Does anyone have any ideal about that?

Thanks

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