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Analog Verification >> Analog Performance Verification >> Revisit the methodology for the offset-simulation of comparators
https://designers-guide.org/forum/YaBB.pl?num=1425669701

Message started by Go,TB on Mar 6^th, 2015, 11:21am

Title: Revisit the methodology for the offset-simulation of comparators
Post by Go,TB on Mar 6^th, 2015, 11:21am

Hello, all

The paper with title “A methodology for the offset-simulation of comparators” posted on this forum has been largely referred for comparator offset simulation setup. Then I have a couple of questions regarding the post-processing methodology inside this paper.

For example, I run 1000-run Monte-Carlo to the comparator with step ramp signal at input. At each ramp step, the comparator will be activated to generate the large signal output (0 or VDD, e.g.). For each run and each step, the input signal voltage value and matched output results are collected.

Then I will wonder if I can characterize the offset voltage by a way other than presented by the paper?

For each run, the value of input signal that can trip the comparator for the first time during the whole input ramp will be recorded. Basically, the input voltage should be the sum of nominal vth + voffset. Then I will have 1000 numbers at hand after simulation. Doing a simple statistical analysis will easily generate the mean value and its 1-sigma value. The mean value is the nominal vth and 1-sigma value the voffset of our interest.

This way we don’t need to go through the complex post-processing as in the paper. Please correct me if my methodology is flawed.

Thanks!

Title: Re: Revisit the methodology for the offset-simulation of comparators
Post by weber8722 on Mar 18^th, 2015, 7:38am

Hi,

I also think that just using the sample stddev of the measured crossing points is usually enough. By looking to normal quantile plot you can check if you really have a normal Gaussian distribution. Calculating blindly the stddev should give the same results - if you really have normal distributed data, which is usually the case anyway.

If you run a full MC analysis with both process and mismatch variations, then a bad design may give non-normal data. I have seen this also in a conf paper from Intel on a USB trip point (true fab data used with 4000 points).

In such normal-case you Cpk might be e.g. 2.0 but actually the yield is lower than expected acc. to err-function relationship of Cpk vs Y!! :-/

Bye Stephan

Title: Re: Revisit the methodology for the offset-simulation of comparators
Post by Go,TB on Mar 18^th, 2015, 11:02am

I think you make a good point why the post-processing is necessary. The methodology presented by the paper can deliver more information than just blindly doing statical processing after simulation. Thanks for your reply!

weber8722 wrote on Mar 18^th, 2015, 7:38am: