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Simulators >> Circuit Simulators >> PLL specre simulator settings cause deadzone?
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Message started by Jeffrey987 on Mar 10^th, 2015, 4:54pm

Title: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 10^th, 2015, 4:54pm

Hi,

I'm encountering a weird problem in my 2nd order filter integerN PLL.
Situation: The PLL i'm designing (transistor level) is composed of a PFD, (with buffers) charge pump with opamp as bootstrap, RC C filter and LC tank VCO. A x64 is performed. (Fvco = 2.4GHz)

Depending on the settings of the transient simulation, the PLL shows a limit cycle beahvior that is similar to deadzone. As shown in the figure, the control voltage (AND phase!!!) shows jumps (both Vc and phase jumps as the phase should be the integrated one of Vc).

Setting 1: traponly, 5ps maxstep, conservative -> limit cycle
Setting 2: traponly, 0.5ps maxstrep , conservative -> no limit cycle.

Transient noise on with fmax=30GHz

I use traponly since it gives faster startup times.

When I remove the VCO and place a linear VCO model in the circuit, the cycle is gone with setting 1. An ideal charge pump does not solve the issue. I checked all PFD signals but they are wide enough.

I checked my PFD + charge pump in open loop simulations but no deadzone is present (sweeping time difference between reference clock and fb clock and measuring the average output current.)

The PLL system is stable, checked in many calculations, model simulations...

Sadly 0.5ps timesteps take a long time to simulate several useconds.

Anyone knows what the origin of this problem is?
numerical issues or circuit issue?

Could the simulation settings cause deadzone somewhere. Since the problem is resolved by removing the VCO, have you ever seen deadzone occuring in a vco?

The image shows the control voltage of the VCO and the phase (time difference from VCOout to and ideal 2.4GHz clock)

Thanks in advance

Title: Re: PLL specre simulator settings cause deadzone?
Post by Frank Wiedmann on Mar 11^th, 2015, 1:29am

This might be trapezoidal ringing, which is a numerical problem (see http://community.cadence.com/cadence_technology_forums/f/38/t/27587). You can check by selecting "Turn On Symbols", then "Show All Points" in the Trace Properties form of ViVA.

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 11^th, 2015, 2:06am

I'm talking about the big swings on the control voltage and phase, not the high speed ringing, the fast peaks on the signal are due to the reference spur. The problem is the slow speed (several useconds) cycles. since the reference frequency is 26ns, this is not the same frequency magnitude.

Title: Re: PLL specre simulator settings cause deadzone?
Post by Frank Wiedmann on Mar 11^th, 2015, 2:26am

Sorry, I did not read your post carefully enough. Some sort of dead zone in a VCO might be caused by injection locking. However, the fact that the effect disappears with a smaller maxstep value seems to indicate a numerical problem.

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 11^th, 2015, 3:20am

Any sugestions that I can try? I used other integration methods but the only thing that removes the cycle is reducing the timestep. Is 0.5ps timestep commonly used or is this very low?

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 11^th, 2015, 1:04pm

Can the numerical problems induce deadzone in the VCO because I have never heared aboud deadzone in a VCO... I do not understand this principle of deadzone induction by injection locking?

Title: Re: PLL specre simulator settings cause deadzone?
Post by Frank Wiedmann on Mar 12^th, 2015, 2:10am

Injection locking means that the frequency of a VCO in a certain range is locked to the frequency (or a multiple or fraction of it) of a different oscillator in the circuit that is somehow coupled to the VCO. In this range, the VCO control voltage has very little influence on the VCO frequency, which could lead to some sort of a dead zone.

Regarding the numerical problems, you should not normally use the maxstep parameter to control the accuracy of a Spectre simulation. The preferred mechanism is the errpreset parameter, in special cases you can also use parameters like reltol, relref, vabstol or iabstol. With these parameters, you only reduce the step size where it is required in order to reach the desired accuracy and not over the entire simulation.

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 12^th, 2015, 4:08am

Thanks, I will try this. Have you ever seen a design where the low frequency reference spur on the control voltage causes deadzone in the VCO? The spur on the control voltage is 64x slower than the vco speed. I'm looking weather the ripple is created by a circuit issue or if is is the numerical problem.

Title: Re: PLL specre simulator settings cause deadzone?
Post by sheldon on Mar 12^th, 2015, 5:09am

Jefferey,

It is a little difficult to tell from the waveforms, but it looks like
there is a small spike at the reference frequency riding on top
of the control voltage, which would indicate that there is not a
dead zone issue. You did not provide the VTUNE waveforms for
maxstep=0.5ps so it is hard to compare what is happening.
A couple of things to try:
1) turn off transient noise until the behavior is correct
2) When the behavior is correct, only turn on transient noise after
the PLL has locked
3) Instead of conservative, try moderate with relref=pointlocal
4) Did your models account for the loading of the VCO on the
loop filter when analyzing stability?
5) Finally with the looser tolerances, it just might take longer to
settle. Looking at the plot in the lower left, it seems like the
amplitude of the second peak is a little less than the first.

Sheldon

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 12^th, 2015, 5:34am

Hi Sheldon,

Indeed the reference frequency is on top of the control voltage so the pase detecor and CP do their job. Like Frank suggests, it appears there is deadzone in the VCO. I will simulate the signal again at 0.5ps and plot it. It looks really similar except for the big peaks, the reference clock is stil on top of it but that's due to the PFD/CP principle and is normal.

1) With transient noise disabled, the waveform is still the same (except some small noise).

3) what does this change?

4) yes, the same results are present when an ideal analog buffer (vcvs) is placed between the loop filer and the vco so loading is not the problem. The model is s-domain and thus does not takes spurs into account.

5) no the peaks remain and do not reduce in size

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 12^th, 2015, 7:42am

Comparisation

Title: Re: PLL specre simulator settings cause deadzone?
Post by sheldon on Mar 12^th, 2015, 5:32pm

Jeffrey,

Strange. Whatever it is, dead zone does not seem to be the issue.
The little spikes at the reference frequency show that your PFD is
working and that the loop is active.

Again, why don't you try turning off maxstep, using error preset
moderate with relref=pointlocal. This will provide some insight
more insight into the issue.

Some other questions:
1) Does the PLL frequency change with maxstep? It looks like the
average values of VTUNE are different for the two simulations?
2) What is the input common mode range of the VCO? Is 0.5V
volts in the middle of the range or at the lower end of the
common mode range?
3) Is there a pre-scaler or a divide by 2 to generate quadrature
at the VCO output?

Sheldon

Title: Re: PLL specre simulator settings cause deadzone?
Post by sheldon on Mar 12^th, 2015, 6:12pm

Jeffrey,

Another suggestion that addresses the basic issue would be
to go back a few versions and use the Noise Aware PLL flow
to generate a VCO model and use it for transient noise
simulation. There is a meter you can attach to the output
to plot the phase noise.

Sheldon

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 13^th, 2015, 12:13am

Hi Sheldon,

I've seen this presentation online, I seem to do things wrong because this wont work. Is there somewhere a detail description how this flow works?

Title: Re: PLL specre simulator settings cause deadzone?
Post by Ken Kundert on Mar 13^th, 2015, 1:31pm

You seemed to have dismissed out of hand Frank's initial suggestion that trapezoidal rule ringing might be causing the problem. Did you at least check to see if trapezoidal rule ringing is a problem? I suggest that you should examine the supply currents and make sure they are clean.

It may be that your loop is border-line unstable. Have you performed a stability analysis?

You should also turn off the noise sources until you get this issue resolved.

-Ken

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 13^th, 2015, 3:05pm

Hi Ken

- Yes I checked for trapezoidal ringing but it's not there on the supply (see image, however currents are large 10mA). However I DO see ringing on the frequency of the VCO. This is no PLL spur or something.

- It would supprise me that the loop is unstable, I modelled it such that the phase margin is 65° and with an ideal VCO with the same Kvco it works fine, the startup response is damped well. I tried changing the Kvco of the verilogA VCO (160MHz/V - 320MHz/V, nominal 240MHz/V) but the system became not unstable (a bit less stable lets say).

- Can I do a stability analysis in the phase domain? I usually watch the step response or rely on my model. Have to be sure the system is stable of course.

my simulator settings now:
maxstep=5 ps
reltol=100e-6
abstolV=1µV
abstolI=1pA
errpreset=conservative
method=traponly
relref=alllocal
APS enabled but specre disables multithreading
use ++aps
circuit preset PLL.

In the log file, at the beginning there are notices about trapezoidal rining found in the subcircuit of the inductor. I tried different convergence parameter settings but does not improve. Only setting the relref to pointlocal improves the accuracy but slows down the simulation even beyond the time it runs at 0.5ps...

Any comments?

Thanks already for you help on this problem! I will do my best to provide as much information as possible.

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 13^th, 2015, 4:04pm

I've identified a ringing problem in the currents of the varactor. See image. Currents are very large peaks (0.5A).

What is usual the way of tuning the convergence parameters (abstolV,abstolI, lte, errpreset, reltol)? Since there are many combinations possible, randomly reducing some rumbers do not make sense.

Title: Re: PLL specre simulator settings cause deadzone?
Post by Ken Kundert on Mar 13^th, 2015, 8:39pm

Normally, people just use the default tolerances (have you tried that?). If they feel they need more accuracy, they tighten reltol. If they feel that the simulator is misbehaving, they would switch errpreset to conservative. Generally it is not a good idea to play most of the other simulator settings unless you know what you are doing. Doing so often creates more problems than it solves. In particular, it is generally a bad idea to try to control accuracy with maxstep: it is a poor accuracy control.

If I were you I would focus the current spikes on the capacitors. Those seem very unusual and might be another symptom of the underlying problem.

I was suggesting you do a stability analysis because I can think of only two things that would cause the behavior you are seeing: an unstable loop or a deadzone. Like you, I am sceptical that it is a stability problem because the to-lock response seems well damped, but it is hard to be certain with the limited results. If you wanted to try this, you would use a pstb analysis on the loop.

I am also at a loss to see how the VCO could cause a deadzone. Is it a full transistor level VCO or is it a behavioral model?

Have you turned off the transient noise sources?

-Ken

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 14^th, 2015, 12:22am

Thanks Ken!

Yes, The VCO is full transistor when the limit cycle is there. All are RF transistor models from the PDK. The transient noise is off. So with the transistor circuit of the VCO, (Kvco~240MHz/v), the circuit has the limit cycle. With the VerilogA model (from the ahdllib-vco), the circuit dont.

The problem is that when I do not put maxstep below something like 10ps my VCO wont start (even after injecting a current pulse it damp)... This is why I do this.
I can try pstb but then I would require to do a pss first and failed when I did this the first time, the N-ratio is 64 and pretty high for PSS to converge. Are there other analysis I could do to check this behavior? eg vco only tests. A PSS/PNOISE on the VCO does not show any porblems.

The VCO is a PMOS/NMOS corss coupled pair, with pmos current source on top and decoupling capacitor between the current source common mode point and ground and nwell varactors.

I checked a lot of times to see if there is deadone in my pfd/chargepump, I even tried an ideal PFD model and CP but doesnt change anything so I guess the CP and PFD work fine without deadzone. (sweeping time difference beteen ref and fb and measuring the average output current of the charge pump, so pfd with buffers and CP).

Title: Re: PLL specre simulator settings cause deadzone?
Post by Ken Kundert on Mar 14^th, 2015, 12:55pm

Starting oscillators is one of the few valid reasons to use maxstep, but generally you only want to set it to provide about 10-20 steps per cycle. The idea is to make it easier for the oscillator to start without slowing the simulation once it starts. So in your case, a maxstep of 20-40ps should be sufficient. If you are having trouble starting your oscillator with maxstep set to 10 steps per period, you are probably not starting it correctly. Many people try to start an oscillator by perturbing the supply. This generally does not work very well because the oscillator is designed to reject variations in the supply. This is particularly true with differential oscillators. You are better off injecting a signal directly into the resonator that is well coupled into the mode of oscillation.

I don't recommend you run a stability analysis. As you say, it can be a fair amount of work to get it to run and it is unlikely to help. And it will certainly not run with that oscillation present.

My recommendation is to explore the current pulses. You might want to plot the voltage and current waveforms (zoom in so that an individual pulse can be examined in detail). Also, you might want to show us the varactor model.

-Ken

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 14^th, 2015, 2:24pm

Thanks alot Ken,

Im now simulating without maxstep.

-With reltol=1e-3 it wont start, I inject 1mA for 100ps to a oscillation node and not the supply.
with reltol1=1e-6 it does start, with pointlocal method. Now the simulation steps are automatically xxx fseconds. Results from 1e-5 and 1e-6 reltol shown and do not show a limit cycle. Only You can see the detail simsettings in the logfile. Still there are warnings about ringing. Further decrease this value until they are gone?

-So this is is the correct way to work to tighten te simulation accuracy? (I do not use any errpresets)

-What advice can you give me on the different methods on pointlocal, alllocal... I understand from the spectre manual what they mathematically do but I do not understand the effect of them? Should I try different things or leave it unchecked? Pointlocal forces the steps smal (fs range) while allglobal allows x pseconds step size. Waiting for the results on this.

-It is correct to use traponly or should I uncheck this to defaults (I read gear methods overdamp the system such that the oscillator does not run).

-The varactor models I cannot show... (pdk content)

Title: Re: PLL specre simulator settings cause deadzone?
Post by Ken Kundert on Mar 14^th, 2015, 6:41pm

I do not believe you are doing a good job starting your oscillator. The oscillator should start with default tolerances.

Here is how to start a resonant oscillator:
1. Set maxstep so that you will get at least 10 steps per cycle but no more than 20 (this is optional)
2. Apply damped sine wave to the resonator (either voltage or current, which ever is more convenient). The built-in sinusoidal sources accept 'damp', a damping factor parameter, when present the amplitude goes to zero with a time constant of 1/damp.
a. choose the frequency to equal the resonant frequency of the resonator.
b. choose the amplitude to be as large as possible without being unreasonable.
c. choose the damping factor so that the oscillator starts quickly with default tolerances. Try not to overdrive the oscillator.

You should not be adjusting the secondary accuracy settings unless you know what you are doing. This includes relref and method. Instead, you should follow the following algorithm:
1. Start with the default tolerances (always do this). That means, that all of the tolerance and accuracy settings should be left unspecified (reltol, vabstol, iabstol, method, gmin, errpreset, relref, etc.). To be clear, the default tolerances are reltol=0.001, vabstol=1uV, iabstol=1pA; view the logfile to assure that these are being used.
2. Simulate.
3. Examine the results. If they look good, you are done. If they are not accurate enough, tighten reltol. If the simulator seems to be misbehaving, set errpreset=conservative. If you see point-to-point ringing in your results (check the supply currents), set method=gear2only.
4. Go to step 2

relref=sigglobal is the default. It is adequate when all signals levels are roughly the same size, as in your circuit.
relref=alllocal is used when the signals are badly scaled. This can happen if you use behavioral models. For example, if in your circuit you were to write a frequency meter that output the VCO frequency in volts, then it would appear as if there were a 2.4GV signal present in your circuit. In this situation you would use relref=alllocal. You can determine if this is this is needed by setting the 'diagnose' option. It will tell you the largest voltage found anywhere in the circuit. If it is much larger than Vdd, then you should either use errpreset=conservative (recommended) or relref=alllocal.
Never use relref=allglobal, it is too loose. I don't recommend relref=pointlocal. I have never seen a situation where it was called for.

You should still try to understand the situation with the varactor currents. If you like, you can email the varactor model directly to me and I will look to see if it has any of the common problems. PDKs are notorious for having problematic behavioral models.

-Ken

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 15^th, 2015, 4:40am

Thanks Ken,

I will follow these steps carefully, the VCO starts with the damped sinewave (now 1ns constant @ 4mA, The VCO has bias of 5mA with 30ps maxstep and no other settings). Monitorred the current injection and fades away like expected.

I did already notice small p2p ringing with trap (see image) so switched to gear2only (VCO runs) but pikes on the varactor are still there on gear2only method. switching to conservative makes the VCO output signal clean.

The model of the varactor I cannot share because it is a real fab pdk. Could it be that it is a charge based model and KCL is violated at some points? If you measure the subcircuit of the varactor, there seem to be charge generated (peak currents of 200mA in 1 step) that does not flow out of the external pins of the varactor (only 2 pin model without bulk, RF_varactors with bulk show same result but are more complex). Current into Node 1 of the intenal source is a positive while node 2 of the internal source of the varactor is a negative current (~200mA) so current flows through the source. However at higher subckt level, no currents are measured at the varactor nodes so the current somehow vanished. There are no other sources or components parallel so something goes wrong here.

edit:

The pikes on the varactor current are gone when disabling the ++aps. However at normal reltol the limit cycle is still there but now it is a linear (very straight) rising and falling signal on Vc with a period of a few useconds (with the spur on top).

-Jeffrey

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 15^th, 2015, 7:55am

Update:

Since it is not improving, I decided to strip down the PLL and replace ideal components. An ideal CP (vcvs) and PFD and divider (verilogA) and only a real VCO. As on previous post, the control voltage just goes lineary. The phase shows jumps and the frequency is instable.

method: gear2only + conservative

-Jeffrey

ps: The Vc is a zoomed one, in the beginning it shows a clean acquisition.

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 15^th, 2015, 8:16am

extra on previous post

Title: Re: PLL specre simulator settings cause deadzone?
Post by Ken Kundert on Mar 15^th, 2015, 12:38pm

If current is just disappearing, and it reappears when you disable APS, then you should contact Cadence.

Until then, you might try replacing the varactor. You could try using the one given in Modeling Varactors.

-Ken

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 15^th, 2015, 1:10pm

Yes, It is not completely disabling aps what i've done.
You can enable aps but also an option ++aps in the aps configuration tab. selecting and deselection changes the pikes in the varactor.

finally, I did it like you proposed and reduced the reltol with other settings default. The limit cycle vanished at 1e-6 tolerance with gear2only/conservative method. at 1e-5 the cycle was already much smaller. The rusults are much more accurate then when I ran it at 0.5ps maxstep

Maybe a final question, do you recommend using the PLL circuit setting in APS?

So we can conclude what I did wrong:

-maxStep should not be used to improve the simulation results of the PLL.
-Do not inject a current pulse but a damped sine to start the oscillator.
-Dont start randomly reducing the other convergence settings.
- ++aps option can result in issues regarding the varactor currents. This can be PDK model dependent.

Thanks alot for your help!

Best regards

Jeffrey

Title: Re: PLL specre simulator settings cause deadzone?
Post by Ken Kundert on Mar 15^th, 2015, 6:43pm

I was not involved with the development of APS, so I cannot really make a recommendation on its use. I expect that APS is a collection of safe algorithms and enhancements to Spectre that speed it up. After all, that is the difference between a circuit simulator, such as Spectre, and a timing simulator, such as Ultrasim. Circuit simulators should use safe algorithms that almost always get the right answers. That is what 'errpreset=conservative' is all about. It forces Spectre to use the safest algorithms.

However, as I said, I was not involved with its development, so I don't know.

It is concerning that me that you are reporting that KCL is not satisfied by APS. However, I suspect that the problem is really with the model. Even safe algorithms can give bad results if the underlying models are bad. That is why I recommend that you contact Cadence. If the problem is with the model, Cadence work with the foundry to get it fixed, and if the problem is the simulator, well, they can fix that themselves.

I am not a big believer in 'magic settings'. It is true that if you really know what you are doing, you can customize the simulator settings to the circuit or the situation and get better results. But most people do not understand the subtleties and just end up getting themselves into trouble. So, just start with the default tolerances. If the simulator misbehaves, try errpreset=conservative, or if you just need more accuracy, tighten reltol.

-Ken

Title: Re: PLL specre simulator settings cause deadzone?
Post by Jeffrey987 on Mar 15^th, 2015, 11:12pm

Great thanks!