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Modeling >> Semiconductor Devices >> MOSFET Spice models question
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Message started by Torq on Dec 23^rd, 2015, 1:33am

Title: MOSFET Spice models question
Post by Torq on Dec 23^rd, 2015, 1:33am

Hi!

I model some digital circuit working with near/under threshold voltage supply, and i doubt about precision of transistor model. I am using TSMC 65nm process, which uses BSIM4.5 Level 54 models. Is it enough for accurate model the under threshold behavior of MOSFET, or i need some better models?

Thanx!

Title: Re: MOSFET Spice models question
Post by Geoffrey_Coram on Jan 4^th, 2016, 5:34am

I think BSIM4 can model subthreshold behavior, but the question is whether the foundry has extracted the model parameters accurately enough for that region. You may also find that you are more susceptible to interconnect parasitics when you operate with a low supply voltage: if there's a lot of parasitic resistance, for example, then the IR drop may push the supply too low.

Title: Re: MOSFET Spice models question
Post by Torq on Jan 4^th, 2016, 12:12pm

Geoffrey_Coram wrote on Jan 4^th, 2016, 5:34am:

I think BSIM4 can model subthreshold behavior, but the question is whether the foundry has extracted the model parameters accurately enough for that region.

Thank you, Geoffrey! I think, you're right, the parameters precision outside the working range is very questionable. From the other hand, the near threshold voltage (NTV) is not something unusual: NOR4 cell, for example, includes 4 pmos between supply and output, so some of that pmos is likely operates at NTV.

Geoffrey_Coram wrote on Jan 4^th, 2016, 5:34am:

You may also find that you are more susceptible to interconnect parasitics when you operate with a low supply voltage: if there's a lot of parasitic resistance, for example, then the IR drop may push the supply too low.

I'm not sure i clearly understand you. But, it seems not possible to design synchronous circuit for NTV supply because of all things you describe.
I'm planning to use asynchronous (delay-insensitive) digital design which is robust to PVT variations (and to the IR-drop in particular). So asynchronous logic must operate at NTV. The only question is how close the simulation to the real silicon life.