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Modeling >> Semiconductor Devices >> TFETs
https://designers-guide.org/forum/YaBB.pl?num=1457351332

Message started by nosrat on Mar 7^th, 2016, 3:48am

Title: TFETs
Post by nosrat on Mar 7^th, 2016, 3:48am

• Is it possible for anyone to help me about TFET HSPICE libraries?
I couldn’t download from https://nanohub.org/publications/12
best regards
Nosrat

Title: Re: TFETs
Post by Geoffrey_Coram on Mar 8^th, 2016, 6:56am

I had no trouble downloading a file from that link, even without logging in. (However, the model itself is capacitance-based, hence non-charge-conserving, and uses $table_model rather than physical equations.)

Title: Re: TFETs
Post by nosrat on Mar 8^th, 2016, 9:42pm

Hi Dear

But I couldn’t download it. Is it possible for you to send the file to me?
I need the TFETs library of HSPICE for analyzing analog circuits. Does the file fulfill my need in your idea?
Would you do me a favor and give me a hand on this one, too? I will really appreciate it.

Title: Re: TFETs
Post by nosrat on Mar 8^th, 2016, 9:48pm

I will send my email address by PM

Title: Re: TFETs
Post by Geoffrey_Coram on Mar 9^th, 2016, 1:53pm

Is your country subject to export restrictions?

But I don't think this file is what you are looking for; it's a compact model, meaning a description of currents and charges (well, capacitances) given applied biases. There is a set of sample parameters, but I wouldn't say it was an "HSPICE library."

Title: Re: TFETs
Post by new on Mar 10^th, 2016, 1:17am

Hai,

Can we use this model file in Cadence Virtuoso for analyzing analog circuits?

Title: Re: TFETs
Post by Geoffrey_Coram on Mar 10^th, 2016, 9:30am

gold -
Do you know what I mean when I say "compact model"?

Your question is analogous to asking

Can we use BSIM4 in Cadence Virtuoso for analyzing analog circuits?

The nanoHUB publication is a compact model, that is, the set of equations for a TFET (like BSIM4 is a set of equations for bulk CMOS). There's a set of parameters, but it's probably a set for a device the researchers were using, and may not be anything close to the TFET devices you want to use.

(I'm not up on Cadence's latest branding campaigns, I know the simulator as "Spectre" not as "Virtuoso." But you should be able to run this model in most analog/spice-like circuit simulators.)

Title: Re: TFETs
Post by gold on Mar 10^th, 2016, 7:54pm

Hai Geoffrey,

Verilog A code in TFET model gives the set of equations for current and capacitance and also for dc and ac simulations. But when I try to use this model for pss and pac analysis, it shows some error. Is it possible to run this model file for mixer and LNA circuits in spice simulator?

Title: Re: TFETs
Post by gold on Mar 10^th, 2016, 8:14pm

Sorry. Verilog A code in TFET model gives the set of equations for current and capacitance and also for dc and tran simulations. I want to find conversion gain for mixer circuit. Is it possible in spice? Can you suggest me?

Title: Re: TFETs
Post by Geoffrey_Coram on Mar 11^th, 2016, 7:41am

Do you get a "hidden state" error?

You should post this issue as a "wish" on nanoHUB. (I suspect the problem is that the model assigns values inside if-statements, but doesn't initialize them. Try setting Ids, Cgd, Cgs, and direction to 0 right after "analog begin" in tfet_master.va)

Title: Re: TFETs
Post by nosrat on Mar 12^th, 2016, 4:43am

Hi Geoffrey
Is your country subject to export restrictions?
about this question I must say I don't know.
But I don't think this file is what you are looking for; it's a compact model, meaning a description of currents and charges (well, capacitance's) given applied biases. There is a set of sample parameters, but I wouldn't say it was an "HSPICE library."
about this I agree with you but I would use Verilog-A lookup table model and convert it to HSPICE in order to perform power consumption analysis

Title: Re: TFETs
Post by nosrat on Jun 8^th, 2016, 12:14am

Hi,
I want to plot/print the characteristic Cgd and Cgs vs Vds for different Vgs by using Verilog –A TFET capacitor table model from https://nanohub.org/publications/12
Could you tell me how to change Verilog –A and do that in hspice

Title: Re: TFETs
Post by Geoffrey_Coram on Jun 9^th, 2016, 9:55am

If you post an HSpice netlist showing how you want to measure Cgd/Cgs for a regular MOS model (eg, BSIM4), I could show you how to adapt that to use the Verilog-A TFET model.

I don't think you'd be changing the Verilog-A, though.

Title: Re: TFETs
Post by nosrat on Jun 11^th, 2016, 5:25am

Thanks Geoffrey ...
I've attached a PDF expressing my problem. would you check it, please?

Title: Re: TFETs
Post by Geoffrey_Coram on Jun 13^th, 2016, 8:24am

So, in the Verilog-A code for the model, do you see:

Code:

real Ids, Cgs, Cgd,Qg, Qs, Qd;

?

Delete Cgs and Cgd from that line, and add these lines:

Code:

(* desc="cgd" *) real Cgd;
(* desc="cgs" *) real Cgs;

Then those values should be available for printing.

Alternately, you could put an ac source on the drain and measure the imaginary gate current in an ac analysis to get Cgd, or put the ac source on the source to get Cgs.

Title: Re: TFETs
Post by nosrat on Jun 14^th, 2016, 2:17am

Thanks a lot Mr. Geoffrey
In the verilog –A code for the model, I have done the changes you asked:

real Ids, Qs, Qd, Qg;
(* desc="Cgd" *) real Cgd;
(* desc="Cgs" *) real Cgs;

And for print command in Hspice, I have used below lines:

.DC Vg 0 0.5 0.001
.print dc Cgd
.print dc Cgs

But after running simulation, this warning appears on ‘file.lis’:
**warning** (cgdntfet.sp:35) Unrecognized output type cgs on line above; The line is ignored.

ac output variable type=s not allowed for transient or dc

So still I couldn’t print them (Cgd , Cgd).

Title: Re: TFETs
Post by Geoffrey_Coram on Jun 14^th, 2016, 6:12am

You need to reference the element - how does the simulator know what you mean by Cgd?

I think you want
.print dc x1:Cgs
.print dc x1:Cgd

For a BSIM4 transistor, you'd have had something like
.print dc m1:cgdb
I asked you to show an example for a BSIM4 transistor so you would look up the proper syntax (which I had to look up for you).

Title: Re: TFETs
Post by nosrat on Jun 15^th, 2016, 3:17am

Dear Mr. Coram

Thanks for your excellent comments

I have done it and gotten Cgd/Cgs –Vg numerical values in output file.lis , but for drawing graphic curve when simulation is completed, I put file.sp in the Avan Wave to see the curve. But then, the Avan Wave stops working. I think this problem happens when we write . print dc xn1:Cgd in netlist. Is it possible to you to help me on this one, too? Sorry for bothering you this much …

Title: Re: TFETs
Post by Geoffrey_Coram on Jun 15^th, 2016, 8:42am

nosrat wrote on Jun 15^th, 2016, 3:17am:

Avan Wave stops working.

Sounds like a problem for the vendor ...

but you could try changing .print to .plot, if you're trying to get a plot.

Title: Re: TFETs
Post by zeropond on Apr 6^th, 2017, 9:38am

Hello :)
I am zeropond. I am a new member of this forum site. But, I have only known that the TFET is tunnel field effect transistors are those transistors which interest band to band tunneling. In tunneling band to band is formation when electron in the valence band semiconductor tunnels accros band gap of the conducting band without traps.
Thank You :)