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https://designers-guide.org/forum/YaBB.pl Other CAD Tools >> Entry Tools >> Generating Verilog netlist from Schematic in IC61 using NC-Verilog https://designers-guide.org/forum/YaBB.pl?num=1466094202 Message started by ic_engr on Jun 16th, 2016, 9:23am |
Title: Generating Verilog netlist from Schematic in IC61 using NC-Verilog Post by ic_engr on Jun 16th, 2016, 9:23am Hello I am trying to generate Verilog netlist from schematic in IC 6.1 using NC-Verilog. I am getting the following errors: *Error* evalalias: a macro must be defined before its use - (hnlSetOutputVars) In the Netlist Set-up I am setting stop view as "symbol" since I dont want it to netlist transistors. Any idea what may be causing this. Regards ic_engr |
Title: Re: Generating Verilog netlist from Schematic in IC61 using NC-Verilog Post by Andrew Beckett on Dec 29th, 2016, 2:07am This was a bug which was fixed in IC617, and happened if you used ADE first and then the Verilog netlister later within the same session. See https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000005xHB5EAM&pageName=ArticleContent&sq=005d0000001T3WNAA0_2016122910610824 Regards, Andrew |
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