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Design >> Analog Design >> Settling in a Pipelined ADC
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Message started by rabeh4 on Jul 9^th, 2016, 2:49pm

Title: Settling in a Pipelined ADC
Post by rabeh4 on Jul 9^th, 2016, 2:49pm

Dear All,

As we know that from theory in a Pipelined ADC each stage must be settled within half of the clock period. Say, the ADC I am designing has a sampling frequency of 50MSPs which equals a period of 20 nS. So theoretically each stage must be settled within 10 nS i.e. in less then half of the clock cycle. I thought a lot about it but did not understand it completely. How can I make sure that each stage has been settled within half of the clock cycle ? How can I test it ?

Regards

Title: Re: Settling in a Pipelined ADC
Post by Mos on Aug 29^th, 2016, 2:24pm

You have to make sure that you have settled with the required resolution
This thesis discussed the linear settling part of it on page 26
http://www.eecg.utoronto.ca/~johns/nobots/theses/pdf/2008_ahmed_phd.pdf

Title: Re: Settling in a Pipelined ADC
Post by sheldon on Oct 29^th, 2016, 6:17am

Rab4,

Not sure I understand the question. You put in a full scale step and
simulate. Allow a lot longer than required to allow the circuit to settle
fully. Then measure the time point where the output is a 1/2 lsb
different than final settled value. The other thing is do you really
that tight a settling, doesn't bit overlap relieve the settling requirements.

Sheldon

Title: Re: Settling in a Pipelined ADC
Post by Mos on Sep 23^rd, 2018, 9:23am

Hi Sheldon,
I think the bit-overlap helps in easing the design of flash in pipeline datapath. But any error in DAC is the error in overall ADC resolution.
So the DAC typically needs to be as accurate as the ADC itself. But this relaxes as we go down the stages.