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Analog Verification >> Analog Functional Verification >> If statement VerilogA
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Message started by verilogGuy on Jul 11^th, 2016, 1:17pm

Title: If statement VerilogA
Post by verilogGuy on Jul 11^th, 2016, 1:17pm

Hi, what does an '&' in an if statement in verilogA mean? When does the following return true:
for (bit=0;bit<`NUM_DAC_BITS; bit=bit+1) begin
if (code & code_mask[bit]) begin

where 'code' increments after the for loop has run for all NUM_DAC_BITS. code_mask[bit] = 1,2,4,8,16,32,64,128 for i = 0...7. code = 1...255.

Title: Re: If statement VerilogA
Post by verilogGuy on Jul 11^th, 2016, 2:33pm

Sorted it! Brain dead this evening. Returns true when both bits are 1.