The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Analog Verification >> Analog Performance Verification >> EMIR analysis using Cadence's Voltus Fi tool https://designers-guide.org/forum/YaBB.pl?num=1473489882 Message started by vroy_92 on Sep 9th, 2016, 11:44pm

Title: EMIR analysis using Cadence's Voltus Fi tool Post by vroy_92 on Sep 9th, 2016, 11:44pm In the iterated method of EMIR analysis using Voltus Fi, is the first simulation done on the DSPF netlist by eliminating all parasitic resistors and capacitors, or just the resistors are eliminated or the tool tries to lump the smaller RC segments into larger RC to get a similar circuit behavior?

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