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Analog Verification >> Analog Performance Verification >> Simulating noise from slow clocked reset
https://designers-guide.org/forum/YaBB.pl?num=1486502523

Message started by simsim on Feb 7^th, 2017, 1:22pm

Title: Simulating noise from slow clocked reset
Post by simsim on Feb 7^th, 2017, 1:22pm

Hi all,

I have an amplifier whose output is sampled at 30 kHz. However I apply a reset signal to the amplifier at slower frequency. The reset frequency is configurable, but 100 Hz is a good refresh rate. What would be a good simulation to capture the slow reset noise.
For example, running a pss analysis with beat frequency 100 Hz, and pnoise with frequency span 15 kHz?

Thanks,
Mohit