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Design Languages >> Verilog-AMS >> Custom Bit sequence in verilog-ams
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Message started by bit_an on Apr 10^th, 2017, 2:18pm

Title: Custom Bit sequence in verilog-ams
Post by bit_an on Apr 10^th, 2017, 2:18pm

Hello,

I want to generate a specific bit sequence (in verilog ams) for testing my system. Also with specific rise time and variable pulse width. Is there any reference for such operation?!

Thanks

Title: Re: Custom Bit sequence in verilog-ams
Post by Ken Kundert on Apr 10^th, 2017, 8:07pm

You might want to take a look at the random bit stream generators found at the Verilog-AMS page.

-Ken