The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Other CAD Tools >> Physical Verification, Extraction and Analysis >> Post Layout Simulation For Mixed signal Verification Environment
https://designers-guide.org/forum/YaBB.pl?num=1499422607

Message started by Gp on Jul 7^th, 2017, 3:16am

Title: Post Layout Simulation For Mixed signal Verification Environment
Post by Gp on Jul 7^th, 2017, 3:16am

Hi All,

I know the Mixed signal verification Environment. Now, I want to do the Post Layout Simulation of this Mixed signal environment. So, What is the flow for Post Layout Simulation particular for the Mixed signal environment?
Kindly give the steps for this procedure in cadence tool.

Title: Re: Post Layout Simulation For Mixed signal Verification Environment
Post by deba on Jul 10^th, 2017, 6:32am

By mixed signal I assume that you are referring to irun based AMS simulation. Doing a post layout simulation in such an environment would be very time consuming. Moreover, I don't think it will be of significant help as the digital post layout simulations are taken care separately by the dedicated tools. The point of running mixed signal is to ensure only functional verification.

Title: Re: Post Layout Simulation For Mixed signal Verification Environment
Post by DanielLam on Jul 10^th, 2017, 10:06am

Hi,

I'll have to disagree with deba about the "The point of running mixed signal is to ensure only functional verification.".

Post layout simulation is to ensure functionality, and to see how much performance is affected. One example of post layout sim is to see how much slower a SAR ADC has become due to capacitive parasitics. In a mature technology, if we're not hitting the speed spec in post layout C sims, we're not going to hit it in measurements. So we will adjust the layout, or schematic if necessary. Extract, and sim again.

Another example might be capacitive coupling onto a sensitive analog line. Functionally the circuit might work, but maybe the signal-to-distortion ratio dropped by 6 dB and you don't know why. It's important to check specifications.

Anyways, the flow goes something like:
1) Schematic sim results
2) C-extracted sim results, compare with schematic, adjust any major parasitic issues
3) RCC sim, compare with schematic, adjust any major parasitic issues

Now people have varying opinions on the accuracy of RCC sims, whether or not the extraction tool worked correctly or not. The C sim is usually all right, the RCC can sometimes be misleading.

Depending on the size of your extraction, you might also consider parasitic reduction to reduce file size (usually only for RCC).

Title: Re: Post Layout Simulation For Mixed signal Verification Environment
Post by Maks on Jul 19^th, 2017, 8:06am

This step - improving layout when post-layout simulation results differ from schematic simulations, and are out of spec - may be very time consuming (especially in advanced nodes). Finding out what is causing the problem - which parasitic elements, what layer, what area of the layout - is not easy. Luckily, there are some new tools that can help with that.

Theoretically, RC (or RCC) extraction mode is the most accurate (assuming you don't have L or mutual L problems in your design). Practically, there are many potential issues, such as:

1. standard C extraction tools may ignore some small but critical capacitive coupling (such as victim-aggressor) - here, using field solver for critical nets may help greatly. For example - to verify capacitance matching or weighting for SAR ADC (especially with small unit cap, such as 1-2 fF or below).

2. some (industry standard) extraction tools are known to mess with R extraction. Such as creating disconnected R network for connected net - and shorting them by small resistors at arbitrarily selected nodes (!).

3. R network can be completely wrong when doing so-called hierarchical extraction (i.e. doing black-boxing or grey-boxing of some cells), or when having p-cells that are black-boxed - multiple connection points on the layout (i.e. for power nets) are reduced to one pin/port, with shorting of all these points - obviously, higher hierarchy level net will have a wrong R network.

4. RC reduction in most modern extraction tools is targeting timing simulation, it can omit some small but important capacitive couplings, and in general generate an RC network not accurate enough for analog designs (but perfectly fine for digital designs).

5. etc. etc. etc.

Max