The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> Convergence errors https://designers-guide.org/forum/YaBB.pl?num=1505948065 Message started by Lieutenant Columbo on Sep 20th, 2017, 3:54pm

 Title: Convergence errors Post by Lieutenant Columbo on Sep 20th, 2017, 3:54pm What are convergence errors and how do I avoid them?

Title: Re: Convergence errors
Post by Ken Kundert on Sep 20th, 2017, 4:52pm

The simulator does not directly calculate the solution at a particular time point. Rather it uses an iterative procedure where it guesses a possible solution, checks to see if it sufficiently satisfies Kirchhoff's laws, and if not, refines the guess and tries again. A convergence error occurs when that iterative process does not converge to a specific value.

Doing things like changing errpreset or changing the integration method or changing the tolerances can make convergence problems go away, but it is often happenstance. Meaning that making the change did not eliminate the problem that is causing the non-convergence, but rather simply causes the problem to be avoided for that particular simulation. In this case, the problem can easily resurface if you make some other seemingly unrelated change to the circuit or simulation.

Convergence issues occur when a discontinuity combines with feedback. Consider a Verilog-A block that contains an if statement such that if the input to the block is greater than zero it produces an output that is less than zero and visa versa.  Something like this:

Code:
 if (V(in) > 0)        V(out) <+ -1;    else        V(out) <+ +1;

Now, connect the output to the input. The if statement provides the discontinuity and connecting the output back to the input provides the feedback.  This situation causes nonconvergence and the value of the signal flips back and forth between +1 and -1 forever. If you were to get rid of the feedback, the problem goes away. One way to get rid of the feedback is to add some delay. As long as there is no feedback over a time step, you are okay.  Specifically, if you connect the output to the input with a delay of 1us, then as long as the timestep is smaller than 1us there is no feedback and so the system would converge without difficulty.

With electrical components such as resistors and capacitors, the current is written as a function of voltage (or visa versa). If there is a discontinuity in the IV characteristics you have a potential problem. If you connect the resistor or capacitor directly across an ideal voltage source, then the voltage would be independent of the current, so there is no feedback, and no convergence problems. However, if you place the component in a real circuit, where the pin voltages would vary with the current through the component, and you now have the feedback, and that combined with the discontinuity causes the convergence problems.

To resolve convergence problems, particularly when using functional models, you want to look for discontinuities embedded in feedback loops (think classic feedback loops like with opamps (feedback traverses several nodes), as well as local feedback loops like with source degeneration (feedback traverses only one node)).  Once you identify the potential source of the convergence issue, try removing the discontinuity or the feedback and see if the problem goes a way. If it does, that is a good indication that you have found the source of the problem. Then to fix it, either eliminate the discontinuity or eliminate the feedback.

Actually, you do not always need to eliminate the discontinuity. What you want is to avoid discontinuities that causes the signal to move to a new region.  Consider the above example:

Code:
 if (V(in) > 0)        V(out) <+ -1;    else        V(out) <+ +1;

This is problematic when the output is connected to the input because the if statement divides the space into two regions and then says if you are in one region you should be in the other. Now consider this example:

Code:
 if (V(in) > 0)        V(out) <+ +1;    else        V(out) <+ -1;

This will not cause convergence problems when you connect the output to the input because, even though there is a discontinuity and feedback, the discontinuity does not cause the signal to move to a new region, it keeps it in the same region.

If you cannot find the discontinuity, you can often prevent it from stopping the simulation by adding cmin. This adds a small capacitor to every node. It works because capacitors dominate over resistors when the time step is very small.  If the discontinuity is in a resistor, adding cmin allows the simulator to overwhelm the discontinuity with the linear capacitor by taking small time steps.  This tends to work very well with traditional circuits and less well with functional models.  Unfortunately, adding cmin is unlikely to help if the discontinuity is in a capacitor.

Hope that helps.

-Ken