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Simulators >> AMS Simulators >> how to override the parameter of verilog-a module with array parameter
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Message started by davidshw on Dec 21^st, 2017, 2:35am

Title: how to override the parameter of verilog-a module with array parameter
Post by davidshw on Dec 21^st, 2017, 2:35am

if a verilog-a module has an array parameter, such as

moduel test (A,B)
parameter integer p1[1:4]='{1,2,3,4} ;
analog begin
... ...
end
endmoudle

when instantiating this module in hspice or spectre, how to override the array parameter?
xdut a b test p1=???

Title: Re: how to override the parameter of verilog-a module with array parameter
Post by Andrew Beckett on Dec 21^st, 2017, 7:26am

Assuming you've corrected the spelling mistakes in the VerilogA module, in spectre syntax (for spectre as the simulator) it would be:

xdut (a b) test p1=[5 6 7 8]

Regards,

Andrew.