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Simulators >> RF Simulators >> Phase noise in an inverter
https://designers-guide.org/forum/YaBB.pl?num=1520508817

Message started by deba on Mar 8^th, 2018, 3:33am

Title: Phase noise in an inverter
Post by deba on Mar 8^th, 2018, 3:33am

Hi,

I am trying to simulate the phase noise of inverter using. The setup is attached. I am using Spectrerf tool from Cadence.

Pnoise is run using noisetype=sources. The phase noise is measured at out, out_clip_100m and out_clip_200m. out_clip_100m limits the output waveform within 100 mV to limit the AM noise. Similarly for out_clip_200m. The input is a square wave at 100 MHz, 1.4 V swing.

1) Which of these plots will be seen in the phase noise analyser? out or out_clip_100m/our_clip_200m?

With clipping, the phase noise is much lower and doesn't change with the clipping limits.

2) After integrating the SSB noise plot from 10 kHz to 50 MHz, I get below numbers:

out: 133 fs (for the inverter output which has amplitude noise)
out_clip_100m: 12 fs
out_clip_200m: 11.9 fs

I have also run a pnoisetype=jitter on this circuit. From that simulation, the Je number on the rising and falling edge for the same integration band is 16.06 fs.

Which of these numbers is realistic? If someone has to quote jitter in 10 kHz to 50 MHz, which number should be quoted?

3) During phase noise measurements, do people use a voltage limiter at the output before feeding it to phase noise analyzer?

Thanks