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Design Languages >> Verilog-AMS >> ideal switch convergence problem
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Message started by liletian on Jul 19^th, 2018, 11:36am

Title: ideal switch convergence problem
Post by liletian on Jul 19^th, 2018, 11:36am

I have cadence convergence issue.

I am using an verilog A relay

`include "constants.vams"
`include "disciplines.vams"

module relay (p, n, ps, ns);
parameter real thresh=0; // threshold (V)
output p, n;
input ps, ns;
electrical p, n, ps, ns;

analog begin
@(cross( V(ps,ns) - thresh, 0 ))
;
if (V(ps,ns) > thresh)
V(p,n) <+ 0;
else
I(p,n) <+ 0;
end
endmodule

Then the schematic is as following, but it has convergence issue. Can you please help to see if cadence can have a look on the problem?

The square in the schematic is the relay.

the clock waveform is as following:

It keeps reporting the congergence error as below:

Title: Re: ideal switch convergence problem
Post by liletian on Jul 19^th, 2018, 11:37am

error message

Title: Re: ideal switch convergence problem
Post by liletian on Jul 19^th, 2018, 11:37am

waveform

Title: Re: ideal switch convergence problem
Post by Ken Kundert on Jul 19^th, 2018, 8:50pm

If the switches are open, the capacitor floats.

Title: Re: ideal switch convergence problem
Post by liletian on Jul 19^th, 2018, 9:12pm

how to solve it?

thanks

Title: Re: ideal switch convergence problem
Post by Ken Kundert on Jul 19^th, 2018, 10:18pm

resistors to ground.