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Analog Verification >> Analog Functional Verification >> Help with a verilog-A code
https://designers-guide.org/forum/YaBB.pl?num=1533034464

Message started by sach075 on Jul 31^st, 2018, 3:54am

Title: Help with a verilog-A code
Post by sach075 on Jul 31^st, 2018, 3:54am

Hi,

I am trying to create a verilog-A model consisting of many switches, one end of all of them being connected to a source, and the other end available as a pin. It is required that the switches turn on in sequence after fixed time intervals, with only one switch being on at a time. For this, I have tried something like this.

Code:

module X(capout,gnd);
....
....
vsource #(<some source>) vin(out_temp,gnd);
genvar j,x;
analog begin
@(initial_step or initial_step("dc", "ac", "tran", "xf")) begin
generate i (0, 2) begin
ival = 0 ;
end
end
for ( j = 0 ; j<=2 ; j = j +1 ) begin
@(timer(0,40u)) begin
V(capout[j]) <+ V(out_temp);
for (x=0; x<=2; x=x+1) begin
if (x!=j) begin
ival[x] = 0;
end
end
end
end
generate i (0,2) begin
I(capout[i]) <+ ival[i];
end
end
endmodule

On running this, however, I get the following error.
[i]Error found by spectre during AHDL read-in.
ERROR (VACOMP-2157): "../veriloga.va", line 24: Encountered a contribution statement embedded in an analog event. Remove the contribution statement from the analog event

It seems that the simulator isn't able to assign the voltage to 'capout[j]' for time steps other than the ones when the timer event occurs. In those times, it is required to float the pin. It is for this very purpose that I have assigned the current function a zero value for all other pins.
Is there any way out to resolve this issue?

Title: Re: Help with a verilog-A code
Post by Ken Kundert on Jul 31^st, 2018, 11:23am

Your code is written such that the switch is closed only at the instant of time when the timer function fires. That is what the simulator is complaining about. Probably what you want is something like the following:

Code:

module mux (a, c);
electrical [2:0] a;
electrical c;
integer i;
analog begin
@(timer(0, 40u)) i = (i + 1) % 4;
I(a[0], c) <+ transition(i == 0, 0, 1u) * V(a[0], c);
I(a[1], c) <+ transition(i == 1, 0, 1u) * V(a[1], c);
I(a[2], c) <+ transition(i == 2, 0, 1u) * V(a[2], c);
I(a[3], c) <+ transition(i == 3, 0, 1u) * V(a[3], c);
end
endmodule

If your mux is connected to capacitors, you will probably need to add gmin to each a input to prevent floating nodes.

-Ken