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Simulators >> Logic Simulators >> rc synthesize problem
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Message started by liletian on Aug 23^rd, 2018, 11:08am

Title: rc synthesize problem
Post by liletian on Aug 23^rd, 2018, 11:08am

Hi all

I am trying to test the buf key word in verilog.

The following code had been wrote. It supposed to add buffers between the input signal and output signal.

However, after the synthesize, it generates the following netlist.

What is the problem here? How to use verilog key word?

Thank you

The synthesize command are

set_attribute hdl_max_memory_address_range 100000000

read_hdl -v2001 test.v

set_attribute library sage-x_tsmc_cl018g_rvt_tt_1p8v_25c.lib

elaborate

synthesize -to_generic

synthesize -to_mapped

write_hdl -generic test > test_syn.v

write_hdl -mapped test > test_synth_map.v

Code:
// Generated by Cadence Encounter(R) RTL Compiler RC14.22 - v14.20-s016_1

// Verification Directory fv/test

module test(in, en, out1, out2);
input in, en;
output out1, out2;
wire in, en;
wire out1, out2;
endmodule

Code:
module test(in,en,out1,out2);
input in,en;
wire in,en;
output out1,out2;
wire out1,out2;

bufif0(in,out1,en);
buf(in,out2);
endmodule // buf