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Simulators >> Circuit Simulators >> LC VCO frequency change with change in initial condition
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Message started by Mohsenkma on Sep 15^th, 2018, 7:05am

Title: LC VCO frequency change with change in initial condition
Post by Mohsenkma on Sep 15^th, 2018, 7:05am

Hello everybody,

I simulate a switch-cap LC VCO in 2.4 GHz in 180 nm technology. When I change the initial conditions of output nodes, the frequency and amplitude of the VCO change dramatically in both transient and pss analysis. As an example the frequency changes more than 100 MHz when initial voltage of the positive output node changes from 0.1 V to 1 V. Also, it's a common practice to set initial condition for oscillators to improve start up condition of the oscillator.
Is there something wrong in my circuit or simulation setting? Or it is a normal behavior? How do I have to set the initial condition?

Thanks a lot,

Title: Re: LC VCO frequency change with change in initial condition
Post by Ken Kundert on Sep 16^th, 2018, 9:56pm

Please do not post simulation questions in a design board.

Applying initial conditions to LC resonators is problematic in SPICE simulators.

To apply an initial condition to a capacitor, the simulator adds a voltage source with a 1Ω series resistance in parallel to the capacitor to drive the initial condition on the capacitor. It then runs a DC analysis to determine the initial state of the circuit. But when you also have an inductor parallel to the capacitor, the inductor effectively shorts the capacitor in the DC analysis, preventing the initial condition from appearing on the capacitor. Instead, it drives a large current on the inductor. In effect, trying to add an initial condition on the capacitor end up adding a huge initial condition on the inductor.

When it comes to starting LC oscillators, it is better to use a tickler source. I recommend using a damped sinuosid.

-Ken

Title: Re: LC VCO frequency change with change in initial condition
Post by Mohsenkma on Sep 17^th, 2018, 7:32am

Hello Mr. Kundert,

Thank you for your response.
I was uncertain and didn't know where to post my question: in a design board or in the circuit simulator's section. Anyway, excuse me for inconvenience.
I removed all the initial conditions. I simulated the circuit one time with Vdd carrying a damped sinuosid and another time with pulse shape Vdd with 500 pS rise time. Each simulation results in different frequency and amplitude. The frequency variation of more than 250 MHz was observed. Since it's well known that the frequency is the function of inductance and capacitance of the tank, how this frequency variation can be justified? And what is the true oscillation frequency?
I appreciate your help.
Thank you so much

Title: Re: LC VCO frequency change with change in initial condition
Post by Ken Kundert on Sep 17^th, 2018, 9:11am

Never make Vdd your tickler source. Most oscillators are designed to ignore changes to Vdd. You want to place the source in such a way that it excites the natural oscillation mode of the circuit.

I don't really know what you mean by changing the frequency of oscillation. Can you be more specific.

-Ken

Title: Re: LC VCO frequency change with change in initial condition
Post by Mohsenkma on Sep 18^th, 2018, 5:18am

Hi Mr. Kundert,

First, I put the tickler source at the output node of the VCO. The VCO oscillated with f=2.02 GHz and Vpp=0.729 V. Second, I made VDD my tickler source (a pulsed shape VDD with 500 pS rise time). The VCO oscillated with f=2.267 GHz and Vpp=436 mV. In both cases the DC voltage of the output node of the VCO was equal to 0.721 V. As you told, the correct method of simulation is the first one. My question is that why the frequency of oscillation in the second simulation is different from the first one?

Thank you so much.

Title: Re: LC VCO frequency change with change in initial condition
Post by Ken Kundert on Sep 18^th, 2018, 3:37pm

The method used to start the oscillator should have no effect on the final steady-state behavior (excluding the phase). So one possible answer is that you have not waited until the steady-state regime has been reached. Are you using PSS analysis, or a simple transient analysis? If you are using PSS, are you using harmonic balance or shooting methods?

I is conceivable that your circuit has two stable solutions, but that would be highly unusual to the point of being bizarre. It is more likely that you are simply making a mistake somewhere. You say you have a switched capacitor bank to control the center frequency, is it possible that one of the switches has changed state?

-Ken

Title: Re: LC VCO frequency change with change in initial condition
Post by Mohsenkma on Sep 29^th, 2018, 7:29am

Hi Mr. Kundert,

Thank you for your response and excuse me for my delayed reply.
I have executed a lot of simulations and changed many parameters. Finally, I found that this problem is arisen when relatively big capacitors (e. g. 200 fF) are used in switched-capacitor bank. I changed the capacitors of switched-capacitor bank from MOSCAP to MIMCAP, but the problem still existed. I increased the negative resistance of cross coupled transistors but it didn't help.
I use both PSS analysis (harmonic balance) and transient analysis. I run transient analysis for 10 μsec to be sure that the steady-state regime has been reached. The state of switches doesn't change during the analysis.
I don’t know why big capacitors have such an effect on my circuit but to solve the problem, I use capacitors below 30 fF in the switched-capacitor bank, therefore, the method used to start the oscillator is no more influential on the frequency and amplitude of the oscillation.

Thank you for your consideration,