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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> CIC filter model based on verilog-ams for sdadc, can't work! https://designers-guide.org/forum/YaBB.pl?num=1541060877 Message started by lwzunique on Nov 1^{st}, 2018, 1:27am |
Title: CIC filter model based on verilog-ams for sdadc, can't work! Post by lwzunique on Nov 1^{st}, 2018, 1:27am hi, everyone! I want to make a CIC filter for sdadc based on verilog ams, I realized this model in simulink, and got the right simulation result, but in verilog ams, this model can not work, because the signal in this model will exceeds the limit of simulator. Code:
the model is as follow: input from sdm is +1 and -1 in matlab，so in this verilog ams model，I also using +1 and -1， the reason for this， i think, maybe,the 2’s complement for real digital cic filter' operation. the code for z-delay: Code:
the code for divider: Code:
please help,thanks very much! |
Title: Re: CIC filter model based on verilog-ams for sdadc, can't work! Post by Ken Kundert on Nov 2^{nd}, 2018, 9:40pm I5.net026 ? That is the node whose voltage is going to infinity. Perhaps you should have identified it. You appear to have a string of 4 open loop integrators. Wouldn't you expect their output to go to infinity over time? -Ken |
Title: Re: CIC filter model based on verilog-ams for sdadc, can't work! Post by lwzunique on Nov 3^{rd}, 2018, 12:57am Ken Kundert wrote on Nov 2^{nd}, 2018, 9:40pm:
if input is always >0, integrators will make the result infinity over time, but if the input is -1 and +1, with increase and decrease, the +1 and -1 stream is from sdm_adc's output, +1 means digital 1, and -1 means digital 0. in the matlab simulink model,as shown below: this model works, the result is correct. the difference between verilog-ams model and matlab simulink model is, sdm adc's order and input signal. but cic filter's clock frequency is based each other's sampling frequency. I don't know why? thanks ! |
Title: Re: CIC filter model based on verilog-ams for sdadc, can't work! Post by lwzunique on Nov 3^{rd}, 2018, 12:57am |
Title: Re: CIC filter model based on verilog-ams for sdadc, can't work! Post by Ken Kundert on Nov 3^{rd}, 2018, 11:32pm There is no real point to show us the Matlab results. We won't be able to understand what is wrong with the Verilog-AMS model by looking at the Matlab results. Any DC offset will cause the results to diverge. Perhaps there is a DC offset in the signals you are using in the AMS simulation. -Ken |
Title: Re: CIC filter model based on verilog-ams for sdadc, can't work! Post by vincentleung on Dec 28^{th}, 2018, 6:38pm you dont have to involve cic in your verilog-a modeling. if you really want to check cic filtering together with analog sdm, i suggest you should save the output data of your analog sdm in cadence, and go back to matlab simulink, run a simulation using cic model together with the data you saved in cadence, which is the way i do when designing a delta-sigma adc. |
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