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Design >> Analog Design >> MDAC for Pipeline ADC - Timing Analysis - Part 2
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Message started by repah on Nov 28th, 2018, 5:00pm

Title: MDAC for Pipeline ADC - Timing Analysis - Part 2
Post by repah on Nov 28th, 2018, 5:00pm

Hello,

I am examing this MDAC for a Pipeline ADC and am confused about the style of the notation on the schematic in terms of the switches.

What do they mean ?

The switches say VDD/GND and P2D and P1D.

Does that mean set that point to VDD at P2D and GND at P1D ?

How would I do this ?

Thank you.


Title: Re: MDAC for Pipeline ADC - Timing Analysis - Part 2
Post by DanielLam on Nov 29th, 2018, 12:52pm

If I had to guess, I'm guessing P1d means the switch has Vdd on it (which probably means on). P2d means the switch has Gnd on it (which probably means off).

Title: Re: MDAC for Pipeline ADC - Timing Analysis - Part 2
Post by polyam on Dec 8th, 2018, 4:28pm

VDD and GND are the supply and ground of the switches. If it is a simple transmission gate it means that the bulks are connected to VDD and GND for PMOS and NMOS respectively.
The MDAC essentially works with two non-overlapping clocks and their delayed version.
P1 and P2 are the non-overlapping clocks.
P1D is the delayed version of P1.
P2D is the delayed version of P2.

Hope it's a good guess!

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