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Design Languages >> Verilog-AMS >> DAC Jitter Modeling for CTSD Modulator
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Message started by Ramy_Rady on Apr 19^th, 2019, 8:22pm

Title: DAC Jitter Modeling for CTSD Modulator
Post by Ramy_Rady on Apr 19^th, 2019, 8:22pm

Hello,

I was implementing a 5 bit DAC to be used in a CT sigma delta modulator. I would like to model the error due to clk Jitter at the output of the DAC in VerilogA. Any Ideas?