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Design >> Analog Design >> Continuous time Sigma-delta ADC Integrator area and Fs
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Message started by neoflash on May 25^th, 2019, 8:07pm

Title: Continuous time Sigma-delta ADC Integrator area and Fs
Post by neoflash on May 25^th, 2019, 8:07pm

If noise requirement is the same, which indicates the integrator R shall remain the same.

Also, assume SQNR is much better than circuit noise.

Can we say integrator C will scale linearly with 1/Fs sampling clock? The slower the Fs, the smaller the Cap?

Thanks,
Neo