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Design >> Analog Design >> comparator offset voltage simulation veriloga model
https://designers-guide.org/forum/YaBB.pl?num=1562183339

Message started by Hesham on Jul 3^rd, 2019, 12:48pm

Title: comparator offset voltage simulation veriloga model
Post by Hesham on Jul 3^rd, 2019, 12:48pm

Hi All

I recently published a paper on comparator offset voltage simulation that may be of practical value for you. The paper contains a complete verilog-a model that you can directly use in your testbench. You can find the paper here:
https://doi.org/10.1016/j.mejo.2019.05.004

Title: Re: comparator offset voltage simulation veriloga model
Post by spunky on Aug 26^th, 2019, 4:44pm

Hi, Hesham,

I am very interested to see your verilog-A model for the comparators but I have found your paper is pay-per-view from the given link.
Is that possible for you to post the model here?
I encountered some issue with the behaviour model I built (https://designers-guide.org/forum/YaBB.pl?num=1566861946) and would like to have a good model to use.

Thanks!

Title: Re: comparator offset voltage simulation veriloga model
Post by Hesham on Aug 29^th, 2019, 1:43pm

Hi

Please find the veriloga model attached. Enjoy!

Title: Re: comparator offset voltage simulation veriloga model
Post by Horror Vacui on Aug 30^th, 2019, 6:45am

Just out of curiosity: why didn't you published your results at IEEE? Almost all design engineers have some access to at least a subset of IEEE publications.

Title: Re: comparator offset voltage simulation veriloga model
Post by Hesham on Aug 30^th, 2019, 10:35am

I didn't think about it from this perspective, may be because most universities have access to Elsevier as well.
I like the Microelectronics Journal, and in general I think it is better than most of (not all) IEEE conferences. On the other hand, I don't think the topic of this paper can fit in IEEE journals/transactions.

Title: Re: comparator offset voltage simulation veriloga model
Post by Horror Vacui on Sep 17^th, 2019, 10:16am

It is just not true. I know for sure, that in Germany, Sweden and Hungary (probably more EU nations) cancelled their subscription to Elsevier, due to the rapidly increasing prices, what the public sector do not want to finance any more. Furthermore there are many scientists who boycott Elsevier due to its business practice. Companies will usually pay only for IEEE access - in best case -, but not for other publishers.

Title: Re: comparator offset voltage simulation veriloga model
Post by Hesham on Nov 16^th, 2019, 3:19am

We have Elsevier subscription here in Egypt (we are not a rich country). If what you said is true, I am really surprised that the countries you mentioned canceled their subscriptions.

Title: Re: comparator offset voltage simulation veriloga model
Post by Hesham on Apr 25^th, 2020, 1:28am

I added the fulltext of the paper to Research gate for those who do not have Elsevier subscription.
Fast and accurate technique for comparator offset voltage simulation
https://www.researchgate.net/publication/333072059_Fast_and_accurate_technique_for_comparator_offset_voltage_simulation
Enjoy!

Title: Re: comparator offset voltage simulation veriloga model
Post by Felddo on May 13^th, 2020, 7:33am

Hesham wrote on Aug 29^th, 2019, 1:43pm:

Hi

Please find the veriloga model attached. Enjoy!

Thank you for sharing!