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Design >> Mixed-Signal Design >> Offset cancellation in switched capacitor circuit
https://designers-guide.org/forum/YaBB.pl?num=1562788065

Message started by vm511 on Jul 10^th, 2019, 12:47pm

Title: Offset cancellation in switched capacitor circuit
Post by vm511 on Jul 10^th, 2019, 12:47pm

I was trying to use a capacitive reset switched capacitor amplifier so as to also have offset cancellation. However, I observe that as I keep decreasing the clock rate, the offset sampled starts increasing. It's not very clear to me how the clock rate would impact the offset sampled at the output since the cancellation in based on charge conservation. The feedback capacitors I am using are very small (50fF)

Title: Re: Offset cancellation in switched capacitor circuit
Post by subtr on Dec 13^th, 2019, 6:34am

if you can upload a circuit diagram of what you're doing it would be the best. Are you doing the below?

https://www.google.com/url?sa=i&source=images&cd=&ved=2ahUKEwiilvP367LmAhVHyDgGHXrwBwIQjRx6BAgBEAQ&url=https%3A%2F%2Fwww10.edacafe.com%2Fbook%2FphdThesis%2FChapter-5.2.php&psig=AOvVaw2gCKGZc9qBiDYv3ky92TNl&ust=1576333996349823

Title: Re: Offset cancellation in switched capacitor circuit
Post by vm511 on Dec 13^th, 2019, 6:44am

Hi,
The issue had gotten resolved.
Thanks!