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https://designers-guide.org/forum/YaBB.pl Analog Verification >> Analog Performance Verification >> how to make sdm based fractional pll's transient simulation more accurate? https://designers-guide.org/forum/YaBB.pl?num=1571970292 Message started by lwzunique on Oct 24th, 2019, 7:24pm |
Title: how to make sdm based fractional pll's transient simulation more accurate? Post by lwzunique on Oct 24th, 2019, 7:24pm Hi,everyone! the problem is as following: 1. this fractional pll is based on veriloga. all blocks are veriloga model. 2. charge pump current is Icp=16uA, VCO gain kvco=100Mhz, LPF ’s C1=36pf, R1=100K, C2=3.6pf,R3=65K,C3=1pf。 3.when doing transient simulation,after pll locked, using freq function in viva calculator to measure the vco’s frequency, the frequency‘s fluctuation is about 200khz peak to peak, and the center frequency is 4.8G. it should have fluctuation, but isn't this value too large? which magnitude should this fluctuation should be? if the magnitude is about 10khz or less, what's wrong with my model. the model is as below: PFD code: Code:
CP code: Code:
VCO code: Code:
freq to sin wave conversion code: Code:
DIVIDER code: Code:
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Title: Re: how to make sdm based fractional pll's transient simulation more accurate? Post by lwzunique on Oct 24th, 2019, 7:29pm mash code: Code:
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Title: Re: how to make sdm based fractional pll's transient simulation more accurate? Post by Ken Kundert on Oct 26th, 2019, 11:43am If you are asking other people to help you with your code, you should take a little time and clean it up to make it easy to read. If you are going to create a 5kV signal, be sure to run transient with relref=alllocal or errpreset=conservative. Otherwise the simulator will not control errors on normal sized signals. -Ken |
Title: Re: how to make sdm based fractional pll's transient simulation more accurate? Post by lwzunique on Oct 26th, 2019, 7:18pm Ken Kundert wrote on Oct 26th, 2019, 11:43am:
thanks for reply. after posting this question,I have done a simulation, changing the bandwidth of pll from 100k to 10k, the fluctuation changed from about 150khz to 2khz. which means 100khz bandwidth can't suppress the quantization noise of sdm. so maybe it's not errors in the code that caused bad accuracy, it's bad system parameters that matters. I have always thought it was the code and simulation accuracy caused this fluctuation,it seems to be the mis-understanding of thinking. in my model, vco's output is its frequency ,so 5kv means its freq is 5Ghz, and divider is also frequency domain, after the divider, the freq_to_vol block will change frequency to voltage to form the feedback signal for pfd block. I will change relref and errpreset to check if this can make the result more accurate. |
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