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Measurements >> Phase Noise and Jitter Measurements >> Phase Noise measurement for PLL in closed Loop
https://designers-guide.org/forum/YaBB.pl?num=1573386758

Message started by thewirehead on Nov 10^th, 2019, 3:52am

Title: Phase Noise measurement for PLL in closed Loop
Post by thewirehead on Nov 10^th, 2019, 3:52am

Hello there,
I've been new to this forum, so if this question isn't supposed to be here or is already repeated elsewhere (I have searched all across the forum and I was unable to find the answer) please point me there. Thanks.

My question is that, I have rigged-up PLL schematic at transistor level in 65nm. The PLL is working in all the corners. Now I need to run Phase noise analysis to the complete PLL in closed loop. I'm using Virtuoso 6.17, I tried to run PSS and Pnoise analysis and I faced problem with convergence, I tried it multiple ways failed miserably :'(.
Could someone take a time help me solve this issue ? Where exactly am I doing wrong ? and are there any other methods than just this.

My PLL specs:
Ref Clock : 100MHz,
Output Clock: 10GHz
Charge Pump Current : 100uA

Should I run Phase noise analysis to each block separately and should I add it up ? Please help.

Thank You..

Title: Re: Phase Noise measurement for PLL in closed Loop
Post by Ken Kundert on Nov 10^th, 2019, 8:52pm

Use shooting methods, and set tstab long enough so that the PLL reaches lock before the PSS analysis begins.

-Ken

Title: Re: Phase Noise measurement for PLL in closed Loop
Post by thewirehead on Nov 10^th, 2019, 9:12pm

Thanks a lot Ken, big salute..
You made my day,

I will try this, and get back.

Thanks