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Simulators >> Circuit Simulators >> SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre
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Message started by repah on Nov 20^th, 2019, 12:36pm

Title: SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre
Post by repah on Nov 20^th, 2019, 12:36pm

Hello,

I want to do behavioral simulations using SystemVerilog as opposed to using Verilog-A and Verilog-AMS for Mixed Signal Designs in Cadence Virtuoso/AMS/Incisive/Spectre.

How can I use SystemVerilog files ? Can I use them just as I use Verilog-A or Verilog-AMS files ? Will Cadence Virtuoso/Spectre/Incisive/AMS recognize SystemVerilog and just compile and simulate just as with Verilog-A and Verilog-AMS ? Are there any special considerations in using SystemVerilog with Cadence Virtuoso/Spectre/Incisive/AMS?

I want to run these files in a behavioral testbench within a schematic using blocks in the schematic containing the SystemVerilog files (not from the command line) for modeling something like a PLL, ADC, etc.

Thanks.

Title: Re: SystemVerilog Behavioral Simulation in Cadence Virtuoso/AMS/Incisive/Spectre
Post by Andrew Beckett on Dec 24^th, 2019, 6:49am

You can't use SystemVerilog with Spectre (similarly you can't use Verilog, VHDL, or Verilog-AMS with spectre either, since it requires an event-driven simulator). You can use SystemVerilog with AMS Designer though since that's a mixed-signal simulator, and really there's nothing special you need to do for this. If using ADE, you'd create SystemVerilog textual views, or you can reference external files with a .sv suffix - it just works.

Regards,

Andrew.