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Design >> Analog Design >> How to speed up RJ sim for DLL including Regulator
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Message started by aks on Nov 22^nd, 2019, 5:55am

Title: How to speed up RJ sim for DLL including Regulator
Post by aks on Nov 22^nd, 2019, 5:55am

Hi
I am doing RJ sims for a DLL using PSS/Pnoise analysis. I want to include Regulator in my sims to assess impact of regulator noise (random) on DLL's RJ. But the sims are quiet slow. Any suggestions, how to fasten the simulations in this scenario.

Thanks

Title: Re: How to speed up RJ sim for DLL including Regulator
Post by kumar.g on Dec 3^rd, 2019, 5:07am

You can first simulate just the regulator and extract the noise of the regulated voltage for a time of say 1/low_freq_of_interest. Then use this noise in DC source of the DLL test bench as a piece-wise-linear model.

Title: Re: How to speed up RJ sim for DLL including Regulator
Post by aks on Dec 4^th, 2019, 4:18am

Thanks Kumar.. You mean noise at "low_freq_of_interest" or spot noise at say 1MHz?
Actually I was thinking of using integrated noise over range of freq. of interest which covers (Lowest freq of interest to freqDLL/2) and use it as you mentioned.
But then the DLL must be simulated for long enough time to cover impact of the slow moving noise (pwl) spanning over lowest freq of interest (i.e lowest freq 1M Hz => 1usec!! ) which becomes very lengthy simulation and time consuming.

Thanks

Title: Re: How to speed up RJ sim for DLL including Regulator
Post by kumar.g on Dec 4^th, 2019, 11:33pm

low_fre_of_interest is the lower limit of the PLL noise integration. Like you have mentioned in your post, to include the low frequency noise, you will have to simulate upto 1us. However simulating just the regulator as a standalone should speed up your simulation compared to simulating with the PLL.

Title: Re: How to speed up RJ sim for DLL including Regulator
Post by aks on Dec 9^th, 2019, 2:18am

Thanks Kumar for your response. I think I did not make my point very clear in last post.

What I meant in my earlier post was, first I get the noise generated from regulator (stand alone w/o DLL) and apply the same noise on the DLL supply in a separate test-bench (DLL alone w/o Regulator).
To really capture the impact of noise from Regulator on DLL, I must run the DLL (no Reg) simulation long enough (low_fre_of_interest) since DLL supply has the noise from regulator superimposed.

Thanks